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[DFAPacketizer] Track resources for packetized instructions
This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936 llvm-svn: 371198
This commit is contained in:
James Molloy
parent
adbf1f1abb
commit
bd5b6d09b9
@ -82,20 +82,53 @@ private:
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int CurrentState = 0;
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const DFAStateInput (*DFAStateInputTable)[2];
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const unsigned *DFAStateEntryTable;
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const std::pair<unsigned, unsigned> *DFAResourceTransitionTable;
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const unsigned *DFAResourceTransitionEntryTable;
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// CachedTable is a map from <FromState, Input> to ToState.
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DenseMap<UnsignPair, unsigned> CachedTable;
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// CachedResourceTransitions is a map from <FromState, Input> to a list of
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// resource transitions.
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DenseMap<UnsignPair, ArrayRef<std::pair<unsigned, unsigned>>>
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CachedResourceTransitions;
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// Read the DFA transition table and update CachedTable.
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void ReadTable(unsigned state);
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bool TrackResources = false;
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// State for the current packet. Every entry is a possible packing of the
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// bundle, indexed by cumulative resource state. Each entry is a list of the
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// cumulative resource states after packing each instruction. For example if
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// we pack I0: [0x4] and I1: [0x2] we will end up with:
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// ResourceStates[0x6] = [0x4, 0x6]
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DenseMap<unsigned, SmallVector<unsigned, 8>> ResourceStates;
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public:
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DFAPacketizer(const InstrItineraryData *I, const DFAStateInput (*SIT)[2],
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const unsigned *SET);
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const unsigned *SET,
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const std::pair<unsigned, unsigned> *RTT = nullptr,
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const unsigned *RTET = nullptr);
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// Reset the current state to make all resources available.
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void clearResources() {
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CurrentState = 0;
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ResourceStates.clear();
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ResourceStates[0] = {};
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}
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// Set whether this packetizer should track not just whether instructions
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// can be packetized, but also which functional units each instruction ends up
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// using after packetization.
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void setTrackResources(bool Track) {
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if (Track != TrackResources) {
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TrackResources = Track;
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if (Track) {
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CachedTable.clear();
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assert(DFAResourceTransitionEntryTable);
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assert(DFAResourceTransitionTable);
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}
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}
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assert(CurrentState == 0 && "Can only change TrackResources on an empty packetizer!");
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}
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// Return the DFAInput for an instruction class.
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@ -120,6 +153,15 @@ public:
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// current state to reflect that change.
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void reserveResources(MachineInstr &MI);
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// Return the resources used by the InstIdx'th instruction added to this
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// packet. The resources are returned as a bitvector of functional units.
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//
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// Note that a bundle may be packed in multiple valid ways. This function
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// returns one arbitary valid packing.
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//
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// Requires setTrackResources(true) to have been called.
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unsigned getUsedResources(unsigned InstIdx);
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const InstrItineraryData *getInstrItins() const { return InstrItins; }
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};
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@ -23,6 +23,7 @@
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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@ -72,9 +73,11 @@ static DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
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// --------------------------------------------------------------------
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DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
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const DFAStateInput (*SIT)[2],
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const unsigned *SET):
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InstrItins(I), DFAStateInputTable(SIT), DFAStateEntryTable(SET) {
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const DFAStateInput (*SIT)[2], const unsigned *SET,
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const std::pair<unsigned, unsigned> *RTT,
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const unsigned *RTET)
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: InstrItins(I), DFAStateInputTable(SIT), DFAStateEntryTable(SET),
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DFAResourceTransitionTable(RTT), DFAResourceTransitionEntryTable(RTET) {
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// Make sure DFA types are large enough for the number of terms & resources.
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static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <=
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(8 * sizeof(DFAInput)),
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@ -82,6 +85,7 @@ DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
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static_assert(
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(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput)),
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"(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
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clearResources();
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}
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// Read the DFA transition table and update CachedTable.
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@ -93,16 +97,26 @@ DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
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// for the ith state
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//
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void DFAPacketizer::ReadTable(unsigned int state) {
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unsigned ThisState = DFAStateEntryTable[state];
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unsigned NextStateInTable = DFAStateEntryTable[state+1];
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unsigned ThisStateIdx = DFAStateEntryTable[state];
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unsigned NextStateIdxInTable = DFAStateEntryTable[state + 1];
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// Early exit in case CachedTable has already contains this
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// state's transitions.
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if (CachedTable.count(UnsignPair(state, DFAStateInputTable[ThisState][0])))
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if (CachedTable.count(UnsignPair(state, DFAStateInputTable[ThisStateIdx][0])))
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return;
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for (unsigned i = ThisState; i < NextStateInTable; i++)
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CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
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DFAStateInputTable[i][1];
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for (unsigned TransitionIdx = ThisStateIdx;
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TransitionIdx < NextStateIdxInTable; TransitionIdx++) {
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auto TransitionPair =
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UnsignPair(state, DFAStateInputTable[TransitionIdx][0]);
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CachedTable[TransitionPair] = DFAStateInputTable[TransitionIdx][1];
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if (TrackResources) {
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unsigned I = DFAResourceTransitionEntryTable[TransitionIdx];
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unsigned E = DFAResourceTransitionEntryTable[TransitionIdx + 1];
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CachedResourceTransitions[TransitionPair] = makeArrayRef(
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&DFAResourceTransitionTable[I], &DFAResourceTransitionTable[E]);
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}
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}
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}
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// Return the DFAInput for an instruction class.
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@ -141,6 +155,16 @@ void DFAPacketizer::reserveResources(const MCInstrDesc *MID) {
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DFAInput InsnInput = getInsnInput(InsnClass);
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UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
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ReadTable(CurrentState);
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if (TrackResources) {
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DenseMap<unsigned, SmallVector<unsigned, 8>> NewResourceStates;
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for (const auto &KV : CachedResourceTransitions[StateTrans]) {
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assert(ResourceStates.count(KV.first));
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NewResourceStates[KV.second] = ResourceStates[KV.first];
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NewResourceStates[KV.second].push_back(KV.second);
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}
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ResourceStates = NewResourceStates;
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}
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assert(CachedTable.count(StateTrans) != 0);
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CurrentState = CachedTable[StateTrans];
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}
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@ -159,6 +183,21 @@ void DFAPacketizer::reserveResources(MachineInstr &MI) {
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reserveResources(&MID);
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}
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unsigned DFAPacketizer::getUsedResources(unsigned InstIdx) {
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assert(TrackResources && "getUsedResources requires resource tracking!");
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// Assert that there is at least one example of a valid bundle format.
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assert(!ResourceStates.empty() && "Invalid bundle!");
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SmallVectorImpl<unsigned> &RS = ResourceStates.begin()->second;
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// RS stores the cumulative resources used up to and including the I'th
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// instruction. The 0th instruction is the base case.
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if (InstIdx == 0)
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return RS[0];
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// Return the difference between the cumulative resources used by InstIdx and
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// its predecessor.
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return RS[InstIdx] ^ RS[InstIdx - 1];
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}
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namespace llvm {
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// This class extends ScheduleDAGInstrs and overrides the schedule method
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@ -210,6 +249,7 @@ VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,
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MachineLoopInfo &mli, AliasAnalysis *aa)
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: MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
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ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
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ResourceTracker->setTrackResources(true);
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VLIWScheduler = new DefaultVLIWScheduler(MF, mli, AA);
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}
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@ -224,8 +264,11 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
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LLVM_DEBUG({
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if (!CurrentPacketMIs.empty()) {
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dbgs() << "Finalizing packet:\n";
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for (MachineInstr *MI : CurrentPacketMIs)
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dbgs() << " * " << *MI;
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unsigned Idx = 0;
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for (MachineInstr *MI : CurrentPacketMIs) {
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unsigned R = ResourceTracker->getUsedResources(Idx++);
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dbgs() << " * [res:0x" << utohexstr(R) << "] " << *MI;
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}
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}
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});
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if (CurrentPacketMIs.size() > 1) {
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@ -24,6 +24,7 @@
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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@ -1763,6 +1764,16 @@ HexagonPacketizerList::addToPacket(MachineInstr &MI) {
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void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator EndMI) {
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// Replace VLIWPacketizerList::endPacket(MBB, EndMI).
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LLVM_DEBUG({
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if (!CurrentPacketMIs.empty()) {
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dbgs() << "Finalizing packet:\n";
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unsigned Idx = 0;
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for (MachineInstr *MI : CurrentPacketMIs) {
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unsigned R = ResourceTracker->getUsedResources(Idx++);
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dbgs() << " * [res:0x" << utohexstr(R) << "] " << *MI;
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}
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}
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});
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bool memShufDisabled = getmemShufDisabled();
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if (memShufDisabled && !foundLSInPacket()) {
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29
test/CodeGen/Hexagon/packetizer-resources.ll
Normal file
29
test/CodeGen/Hexagon/packetizer-resources.ll
Normal file
@ -0,0 +1,29 @@
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; RUN: llc -O2 -march=hexagon < %s -debug-only=packets 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; CHECK: Finalizing packet:
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; CHECK-NEXT: * [res:0x8] renamable $r1 = S2_vsplatrb renamable $r0
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; CHECK-NEXT: * [res:0x4] renamable $d1 = S2_vsplatrh killed renamable $r0
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target triple = "hexagon"
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; Function Attrs: nounwind readnone
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define i64 @f0(i64 %a0) #0 {
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b0:
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%v0 = trunc i64 %a0 to i32
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%v1 = and i32 %v0, 65535
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%v2 = tail call i64 @llvm.hexagon.S2.vsplatrh(i32 %v1)
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%v3 = and i32 %v0, 255
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%v4 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v3)
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%v5 = sext i32 %v4 to i64
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%v6 = add nsw i64 %v5, %v2
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ret i64 %v6
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.vsplatrh(i32) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0
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attributes #0 = { nounwind readnone }
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@ -192,7 +192,14 @@ class State {
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const int stateNum;
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mutable bool isInitial;
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mutable std::set<unsigned> stateInfo;
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typedef std::map<std::vector<unsigned>, const State *> TransitionMap;
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struct TransitionInfo {
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// Maps from a resource bitmask in this state to the equivalent resource
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// bitmap in the transitioned-to state. This is a 1-to-N mapping.
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std::vector<std::pair<unsigned, unsigned>> ResourceTransitions;
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const State *S;
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};
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using TransitionMap = std::map<std::vector<unsigned>, TransitionInfo>;
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mutable TransitionMap Transitions;
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State();
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@ -221,9 +228,14 @@ class State {
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions.
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//
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void AddInsnClass(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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std::set<unsigned> &PossibleStates) const;
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// TransitionInfo maps from a resource bitmask B in this state to a resource
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// bitmask B' in PossibleStates. This is a one-to-many (or none) mapping.
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//
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void AddInsnClass(
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std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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std::set<unsigned> &PossibleStates,
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std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const;
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//
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// AddInsnClassStages - Return all combinations of resource reservation
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@ -231,16 +243,17 @@ class State {
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// which are possible from this state (PossibleStates).
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//
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void AddInsnClassStages(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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unsigned chkstage, unsigned numstages,
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unsigned prevState, unsigned origState,
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DenseSet<unsigned> &VisitedResourceStates,
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std::set<unsigned> &PossibleStates) const;
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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unsigned chkstage, unsigned numstages,
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unsigned prevState, unsigned origState,
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DenseSet<unsigned> &VisitedResourceStates) const;
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//
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// addTransition - Add a transition from this state given the input InsnClass
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// addTransition - Add a transition from this state given the input InsnClass.
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//
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void addTransition(std::vector<unsigned> InsnClass, const State *To) const;
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void addTransition(
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std::vector<unsigned> InsnClass, const State *To,
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const std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const;
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//
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// hasTransition - Returns true if there is a transition from this state
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@ -329,11 +342,12 @@ State::State() :
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//
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// addTransition - Add a transition from this state given the input InsnClass
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//
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void State::addTransition(std::vector<unsigned> InsnClass, const State *To)
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const {
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void State::addTransition(
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std::vector<unsigned> InsnClass, const State *To,
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const std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const {
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assert(!Transitions.count(InsnClass) &&
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"Cannot have multiple transitions for the same input");
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Transitions[InsnClass] = To;
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Transitions[InsnClass] = {TransitionInfo, To};
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}
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//
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@ -351,9 +365,11 @@ bool State::hasTransition(std::vector<unsigned> InsnClass) const {
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions.
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//
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void State::AddInsnClass(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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std::set<unsigned> &PossibleStates) const {
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void State::AddInsnClass(
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std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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std::set<unsigned> &PossibleStates,
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std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const {
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//
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// Iterate over all resource states in currentState.
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//
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@ -362,25 +378,26 @@ void State::AddInsnClass(std::vector<unsigned> &InsnClass,
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for (std::set<unsigned>::iterator SI = stateInfo.begin();
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SI != stateInfo.end(); ++SI) {
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unsigned thisState = *SI;
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unsigned ThisState = *SI;
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DenseSet<unsigned> VisitedResourceStates;
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LLVM_DEBUG(dbgs() << " thisState: 0x" << Twine::utohexstr(thisState)
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LLVM_DEBUG(dbgs() << " thisState: 0x" << Twine::utohexstr(ThisState)
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<< "\n");
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AddInsnClassStages(InsnClass, ComboBitToBitsMap,
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numstages - 1, numstages,
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thisState, thisState,
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VisitedResourceStates, PossibleStates);
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AddInsnClassStages(InsnClass, ComboBitToBitsMap, numstages - 1, numstages,
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ThisState, ThisState, VisitedResourceStates);
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for (unsigned NewState : VisitedResourceStates) {
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PossibleStates.insert(NewState);
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TransitionInfo.emplace_back(ThisState, NewState);
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}
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}
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}
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void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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unsigned chkstage, unsigned numstages,
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unsigned prevState, unsigned origState,
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DenseSet<unsigned> &VisitedResourceStates,
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std::set<unsigned> &PossibleStates) const {
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void State::AddInsnClassStages(
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std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap, unsigned chkstage,
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unsigned numstages, unsigned prevState, unsigned origState,
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DenseSet<unsigned> &VisitedResourceStates) const {
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assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
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unsigned thisStage = InsnClass[chkstage];
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@ -438,7 +455,6 @@ void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
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if (ResultingResourceState != prevState) {
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if (VisitedResourceStates.count(ResultingResourceState) == 0) {
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VisitedResourceStates.insert(ResultingResourceState);
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PossibleStates.insert(ResultingResourceState);
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LLVM_DEBUG(dbgs()
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<< "\tResultingResourceState: 0x"
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<< Twine::utohexstr(ResultingResourceState) << "\n");
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@ -456,10 +472,9 @@ void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
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//
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if (ResultingResourceState != prevState) {
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LLVM_DEBUG(dbgs() << "\n");
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AddInsnClassStages(InsnClass, ComboBitToBitsMap,
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chkstage - 1, numstages,
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ResultingResourceState, origState,
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VisitedResourceStates, PossibleStates);
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AddInsnClassStages(InsnClass, ComboBitToBitsMap, chkstage - 1,
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numstages, ResultingResourceState, origState,
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VisitedResourceStates);
|
||||
} else {
|
||||
LLVM_DEBUG(dbgs() << "\tSkipped Add - no resources available\n");
|
||||
}
|
||||
@ -578,17 +593,10 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
|
||||
II = SI->Transitions.begin(), IE = SI->Transitions.end();
|
||||
II != IE; ++II) {
|
||||
OS << "{0x" << Twine::utohexstr(getDFAInsnInput(II->first)) << ", "
|
||||
<< II->second->stateNum << "},\t";
|
||||
<< II->second.S->stateNum << "},\t";
|
||||
}
|
||||
ValidTransitions += SI->Transitions.size();
|
||||
|
||||
// If there are no valid transitions from this stage, we need a sentinel
|
||||
// transition.
|
||||
if (ValidTransitions == StateEntry[i]) {
|
||||
OS << SentinelEntry << ",\t";
|
||||
++ValidTransitions;
|
||||
}
|
||||
|
||||
OS << " // state " << i << ": " << StateEntry[i];
|
||||
if (StateEntry[i] != (ValidTransitions-1)) { // More than one transition.
|
||||
OS << "-" << (ValidTransitions-1);
|
||||
@ -610,8 +618,6 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
|
||||
OS << "// " << numStates << " states\n";
|
||||
OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
|
||||
|
||||
// Multiply i by 2 since each entry in DFAStateInputTable is a set of
|
||||
// two numbers.
|
||||
unsigned lastState = 0;
|
||||
for (unsigned i = 0; i < numStates; ++i) {
|
||||
if (i && ((i % 10) == 0)) {
|
||||
@ -620,11 +626,44 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
|
||||
}
|
||||
OS << StateEntry[i] << ", ";
|
||||
}
|
||||
|
||||
// Print out the index to the sentinel entry in StateInputTable
|
||||
OS << ValidTransitions << ", ";
|
||||
OS << " // states " << (lastState+1) << ":" << numStates << "\n";
|
||||
OS << "};\n";
|
||||
|
||||
// Generate the resource transition table.
|
||||
OS << "const std::pair<unsigned, unsigned> " << TargetName
|
||||
<< "DFAResourceTransitionTable[] = { \n";
|
||||
int N = 0;
|
||||
StateEntry.clear();
|
||||
for (const State &S : states) {
|
||||
for (auto &KV : S.Transitions) {
|
||||
StateEntry.push_back(N);
|
||||
for (std::pair<unsigned, unsigned> &T : KV.second.ResourceTransitions) {
|
||||
OS << "{0x" << utohexstr(T.first) << ", 0x" << utohexstr(T.second)
|
||||
<< "}, ";
|
||||
++N;
|
||||
}
|
||||
}
|
||||
OS << "\n ";
|
||||
}
|
||||
// Add a sentinel entry to terminate the search.
|
||||
StateEntry.push_back(N);
|
||||
OS << "\n {~0U,~0U}\n};\n\n";
|
||||
|
||||
OS << "// " << TargetName << "DFAResourceTransitionEntryTable[i] = "
|
||||
<< "Index of the first entry in DFAResourceTransitionTable for\n";
|
||||
OS << "// the ith transition.\n";
|
||||
OS << "const unsigned int " << TargetName
|
||||
<< "DFAResourceTransitionEntryTable[] = { \n";
|
||||
|
||||
N = 0;
|
||||
for (int S : StateEntry) {
|
||||
OS << S << ",";
|
||||
if (N++ % 10 == 0)
|
||||
OS << "\n ";
|
||||
}
|
||||
OS << "\n ~0U\n};\n";
|
||||
}
|
||||
|
||||
//
|
||||
@ -946,7 +985,9 @@ void DFAPacketizerEmitter::emitForItineraries(
|
||||
if (!current->hasTransition(InsnClass) &&
|
||||
current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
|
||||
const State *NewState = nullptr;
|
||||
current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
|
||||
std::vector<std::pair<unsigned, unsigned>> TransitionInfo;
|
||||
current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources,
|
||||
TransitionInfo);
|
||||
if (NewStateResources.empty()) {
|
||||
LLVM_DEBUG(dbgs() << " Skipped - no new states generated\n");
|
||||
continue;
|
||||
@ -982,7 +1023,7 @@ void DFAPacketizerEmitter::emitForItineraries(
|
||||
});
|
||||
}
|
||||
|
||||
current->addTransition(InsnClass, NewState);
|
||||
current->addTransition(InsnClass, NewState, TransitionInfo);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1000,7 +1041,10 @@ void DFAPacketizerEmitter::emitForItineraries(
|
||||
<< "DFAPacketizer(const InstrItineraryData *IID) const {\n"
|
||||
<< " return new DFAPacketizer(IID, " << TargetName << DFAName
|
||||
<< "DFAStateInputTable, " << TargetName << DFAName
|
||||
<< "DFAStateEntryTable);\n}\n\n";
|
||||
<< "DFAStateEntryTable, " << TargetName << DFAName
|
||||
<< "DFAResourceTransitionTable, " << TargetName << DFAName
|
||||
<< "DFAResourceTransitionEntryTable"
|
||||
<< ");\n}\n\n";
|
||||
}
|
||||
|
||||
namespace llvm {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user