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R600/SI: Emit config values in register value pairs.

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Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
This commit is contained in:
Tom Stellard 2013-04-15 17:51:35 +00:00
parent a44e2e18a1
commit bd67f8cd81
3 changed files with 46 additions and 6 deletions
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19
lib/Target/R600/AMDGPUAsmPrinter.cpp
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@ -19,6 +19,7 @@
#include "AMDGPUAsmPrinter.h"
#include "AMDGPU.h"
#include "SIDefines.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/MC/MCContext.h"
@ -150,7 +151,19 @@ void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
MaxSGPR += 2;
}
SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
OutStreamer.EmitIntValue(MaxSGPR + 1, 4);
OutStreamer.EmitIntValue(MaxVGPR + 1, 4);
OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
unsigned RsrcReg;
switch (MFI->ShaderType) {
default: // Fall through
case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
}
OutStreamer.EmitIntValue(RsrcReg, 4);
OutStreamer.EmitIntValue(S_00B028_VGPRS(MaxVGPR / 4) | S_00B028_SGPRS(MaxSGPR / 8), 4);
if (MFI->ShaderType == ShaderType::PIXEL) {
OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
}
}

22
lib/Target/R600/SIDefines.h Normal file
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@ -0,0 +1,22 @@
//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
/// \file
//===----------------------------------------------------------------------===//
#ifndef SIDEFINES_H_
#define SIDEFINES_H_
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
#endif // SIDEFINES_H_

11
test/CodeGen/R600/elf.ll
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@ -1,7 +1,12 @@
; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=CONFIG-CHECK %s
; CHECK: Format: ELF32
; CHECK: Name: .AMDGPU.config
; ELF-CHECK: Format: ELF32
; ELF-CHECK: Name: .AMDGPU.config
; CONFIG-CHECK: .section .AMDGPU.config
; CONFIG-CHECK-NEXT: .long 45096
; CONFIG-CHECK-NEXT: .long 0
define void @test(i32 %p) {
%i = add i32 %p, 2
%r = bitcast i32 %i to float