From bda396ca51b423d41e517c5c86eab66132b311f9 Mon Sep 17 00:00:00 2001 From: Juneyoung Lee Date: Thu, 4 Feb 2021 00:07:04 +0900 Subject: [PATCH] Revert "[ConstantFold] Fold more operations to poison" This reverts commit 53040a968dc2ff20931661e55f05da2ef8b964a0 due to its bad interaction with select i1 -> and/or i1 transformation. This fixes: https://bugs.llvm.org/show_bug.cgi?id=49005 https://bugs.llvm.org/show_bug.cgi?id=48435 --- lib/IR/ConstantFold.cpp | 59 ++++++------- ...amdgpu-codegenprepare-fold-binop-select.ll | 2 +- test/Transforms/InstCombine/apint-shift.ll | 2 +- .../canonicalize-ashr-shl-to-masking.ll | 2 +- .../canonicalize-lshr-shl-to-masking.ll | 2 +- .../canonicalize-shl-lshr-to-masking.ll | 2 +- test/Transforms/InstCombine/icmp.ll | 4 +- ...nput-masking-after-truncation-variant-a.ll | 4 +- ...nput-masking-after-truncation-variant-b.ll | 4 +- ...nput-masking-after-truncation-variant-c.ll | 4 +- ...nput-masking-after-truncation-variant-d.ll | 4 +- ...nput-masking-after-truncation-variant-e.ll | 4 +- ...dant-left-shift-input-masking-variant-a.ll | 4 +- ...dant-left-shift-input-masking-variant-b.ll | 4 +- ...dant-left-shift-input-masking-variant-c.ll | 4 +- ...dant-left-shift-input-masking-variant-d.ll | 4 +- ...dant-left-shift-input-masking-variant-e.ll | 4 +- .../InstCombine/select-of-bittest.ll | 6 +- .../InstCombine/shift-add-inseltpoison.ll | 12 +-- test/Transforms/InstCombine/shift-add.ll | 12 +-- .../ConstProp/InsertElement-inseltpoison.ll | 2 +- .../InstSimplify/ConstProp/InsertElement.ll | 2 +- .../Transforms/InstSimplify/ConstProp/cast.ll | 4 +- .../InstSimplify/ConstProp/poison.ll | 4 +- .../InstSimplify/ConstProp/shift.ll | 24 ++--- .../vector-undef-elts-inseltpoison.ll | 2 +- .../ConstProp/vector-undef-elts.ll | 2 +- .../ConstProp/vscale-inseltpoison.ll | 16 ++-- .../InstSimplify/ConstProp/vscale.ll | 16 ++-- test/Transforms/InstSimplify/div.ll | 39 +-------- test/Transforms/InstSimplify/rem.ll | 31 +------ test/Transforms/InstSimplify/undef.ll | 87 +++++++++---------- test/Transforms/SROA/phi-gep.ll | 2 +- test/Transforms/SROA/select-gep.ll | 2 +- .../X86/insert-binop-inseltpoison.ll | 4 +- .../X86/insert-binop-with-constant.ll | 42 ++++----- .../VectorCombine/X86/insert-binop.ll | 6 +- unittests/IR/ConstantsTest.cpp | 25 +++--- 38 files changed, 197 insertions(+), 256 deletions(-) diff --git a/lib/IR/ConstantFold.cpp b/lib/IR/ConstantFold.cpp index 03cb108cc48..95dd55237e5 100644 --- a/lib/IR/ConstantFold.cpp +++ b/lib/IR/ConstantFold.cpp @@ -630,7 +630,7 @@ Constant *llvm::ConstantFoldCastInstruction(unsigned opc, Constant *V, V.convertToInteger(IntVal, APFloat::rmTowardZero, &ignored)) { // Undefined behavior invoked - the destination type can't represent // the input constant. - return PoisonValue::get(DestTy); + return UndefValue::get(DestTy); } return ConstantInt::get(FPC->getContext(), IntVal); } @@ -916,7 +916,7 @@ Constant *llvm::ConstantFoldInsertElementInstruction(Constant *Val, unsigned NumElts = ValTy->getNumElements(); if (CIdx->uge(NumElts)) - return PoisonValue::get(Val->getType()); + return UndefValue::get(Val->getType()); SmallVector Result; Result.reserve(NumElts); @@ -1151,21 +1151,23 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, } case Instruction::SDiv: case Instruction::UDiv: - // X / undef -> poison - // X / 0 -> poison - if (match(C2, m_CombineOr(m_Undef(), m_Zero()))) - return PoisonValue::get(C2->getType()); + // X / undef -> undef + if (isa(C2)) + return C2; + // undef / 0 -> undef // undef / 1 -> undef - if (match(C2, m_One())) + if (match(C2, m_Zero()) || match(C2, m_One())) return C1; // undef / X -> 0 otherwise return Constant::getNullValue(C1->getType()); case Instruction::URem: case Instruction::SRem: - // X % undef -> poison - // X % 0 -> poison - if (match(C2, m_CombineOr(m_Undef(), m_Zero()))) - return PoisonValue::get(C2->getType()); + // X % undef -> undef + if (match(C2, m_Undef())) + return C2; + // undef % 0 -> undef + if (match(C2, m_Zero())) + return C1; // undef % X -> 0 otherwise return Constant::getNullValue(C1->getType()); case Instruction::Or: // X | undef -> -1 @@ -1173,28 +1175,28 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, return C1; return Constant::getAllOnesValue(C1->getType()); // undef | X -> ~0 case Instruction::LShr: - // X >>l undef -> poison + // X >>l undef -> undef if (isa(C2)) - return PoisonValue::get(C2->getType()); + return C2; // undef >>l 0 -> undef if (match(C2, m_Zero())) return C1; // undef >>l X -> 0 return Constant::getNullValue(C1->getType()); case Instruction::AShr: - // X >>a undef -> poison + // X >>a undef -> undef if (isa(C2)) - return PoisonValue::get(C2->getType()); + return C2; // undef >>a 0 -> undef if (match(C2, m_Zero())) return C1; - // TODO: undef >>a X -> poison if the shift is exact + // TODO: undef >>a X -> undef if the shift is exact // undef >>a X -> 0 return Constant::getNullValue(C1->getType()); case Instruction::Shl: // X << undef -> undef if (isa(C2)) - return PoisonValue::get(C2->getType()); + return C2; // undef << 0 -> undef if (match(C2, m_Zero())) return C1; @@ -1247,14 +1249,14 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, if (CI2->isOne()) return C1; // X / 1 == X if (CI2->isZero()) - return PoisonValue::get(CI2->getType()); // X / 0 == poison + return UndefValue::get(CI2->getType()); // X / 0 == undef break; case Instruction::URem: case Instruction::SRem: if (CI2->isOne()) return Constant::getNullValue(CI2->getType()); // X % 1 == 0 if (CI2->isZero()) - return PoisonValue::get(CI2->getType()); // X % 0 == poison + return UndefValue::get(CI2->getType()); // X % 0 == undef break; case Instruction::And: if (CI2->isZero()) return C2; // X & 0 == 0 @@ -1368,7 +1370,7 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, case Instruction::SDiv: assert(!CI2->isZero() && "Div by zero handled above"); if (C2V.isAllOnesValue() && C1V.isMinSignedValue()) - return PoisonValue::get(CI1->getType()); // MIN_INT / -1 -> poison + return UndefValue::get(CI1->getType()); // MIN_INT / -1 -> undef return ConstantInt::get(CI1->getContext(), C1V.sdiv(C2V)); case Instruction::URem: assert(!CI2->isZero() && "Div by zero handled above"); @@ -1376,7 +1378,7 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, case Instruction::SRem: assert(!CI2->isZero() && "Div by zero handled above"); if (C2V.isAllOnesValue() && C1V.isMinSignedValue()) - return PoisonValue::get(CI1->getType()); // MIN_INT % -1 -> poison + return UndefValue::get(CI1->getType()); // MIN_INT % -1 -> undef return ConstantInt::get(CI1->getContext(), C1V.srem(C2V)); case Instruction::And: return ConstantInt::get(CI1->getContext(), C1V & C2V); @@ -1387,15 +1389,15 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, case Instruction::Shl: if (C2V.ult(C1V.getBitWidth())) return ConstantInt::get(CI1->getContext(), C1V.shl(C2V)); - return PoisonValue::get(C1->getType()); // too big shift is poison + return UndefValue::get(C1->getType()); // too big shift is undef case Instruction::LShr: if (C2V.ult(C1V.getBitWidth())) return ConstantInt::get(CI1->getContext(), C1V.lshr(C2V)); - return PoisonValue::get(C1->getType()); // too big shift is poison + return UndefValue::get(C1->getType()); // too big shift is undef case Instruction::AShr: if (C2V.ult(C1V.getBitWidth())) return ConstantInt::get(CI1->getContext(), C1V.ashr(C2V)); - return PoisonValue::get(C1->getType()); // too big shift is poison + return UndefValue::get(C1->getType()); // too big shift is undef } } @@ -1441,7 +1443,7 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, // Fast path for splatted constants. if (Constant *C2Splat = C2->getSplatValue()) { if (Instruction::isIntDivRem(Opcode) && C2Splat->isNullValue()) - return PoisonValue::get(VTy); + return UndefValue::get(VTy); if (Constant *C1Splat = C1->getSplatValue()) { return ConstantVector::getSplat( VTy->getElementCount(), @@ -1458,9 +1460,9 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, Constant *LHS = ConstantExpr::getExtractElement(C1, ExtractIdx); Constant *RHS = ConstantExpr::getExtractElement(C2, ExtractIdx); - // If any element of a divisor vector is zero, the whole op is poison. + // If any element of a divisor vector is zero, the whole op is undef. if (Instruction::isIntDivRem(Opcode) && RHS->isNullValue()) - return PoisonValue::get(VTy); + return UndefValue::get(VTy); Result.push_back(ConstantExpr::get(Opcode, LHS, RHS)); } @@ -2343,8 +2345,7 @@ Constant *llvm::ConstantFoldGetElementPtr(Type *PointeeTy, Constant *C, return PoisonValue::get(GEPTy); if (isa(C)) - // If inbounds, we can choose an out-of-bounds pointer as a base pointer. - return InBounds ? PoisonValue::get(GEPTy) : UndefValue::get(GEPTy); + return UndefValue::get(GEPTy); Constant *Idx0 = cast(Idxs[0]); if (Idxs.size() == 1 && (Idx0->isNullValue() || isa(Idx0))) diff --git a/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll b/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll index e0037f0d8e4..bfe83c7a128 100644 --- a/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll +++ b/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll @@ -42,7 +42,7 @@ define i32 @select_sdiv_rhs_const_i32(i1 %cond) { define <2 x i32> @select_sdiv_lhs_const_v2i32(i1 %cond) { ; IR-LABEL: @select_sdiv_lhs_const_v2i32( -; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> , <2 x i32> +; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> , <2 x i32> ; IR-NEXT: ret <2 x i32> [[OP]] ; ; GCN-LABEL: select_sdiv_lhs_const_v2i32: diff --git a/test/Transforms/InstCombine/apint-shift.ll b/test/Transforms/InstCombine/apint-shift.ll index 908aeac0cea..5a351efccfc 100644 --- a/test/Transforms/InstCombine/apint-shift.ll +++ b/test/Transforms/InstCombine/apint-shift.ll @@ -337,7 +337,7 @@ define <2 x i1> @test16vec_nonuniform(<2 x i84> %X) { define <2 x i1> @test16vec_undef(<2 x i84> %X) { ; CHECK-LABEL: @test16vec_undef( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i84> [[X:%.*]], +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i84> [[X:%.*]], ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i84> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; diff --git a/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll b/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll index 8d29372c3a7..ba0d32ee376 100644 --- a/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll +++ b/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll @@ -418,7 +418,7 @@ define <3 x i8> @positive_sameconst_vec_undef1(<3 x i8> %x) { define <3 x i8> @positive_sameconst_vec_undef2(<3 x i8> %x) { ; CHECK-LABEL: @positive_sameconst_vec_undef2( -; CHECK-NEXT: [[RET:%.*]] = and <3 x i8> [[X:%.*]], +; CHECK-NEXT: [[RET:%.*]] = and <3 x i8> [[X:%.*]], ; CHECK-NEXT: ret <3 x i8> [[RET]] ; %tmp0 = ashr <3 x i8> %x, diff --git a/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll b/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll index 40bc4aaab21..445f6406b3d 100644 --- a/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll +++ b/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll @@ -418,7 +418,7 @@ define <3 x i8> @positive_sameconst_vec_undef1(<3 x i8> %x) { define <3 x i8> @positive_sameconst_vec_undef2(<3 x i8> %x) { ; CHECK-LABEL: @positive_sameconst_vec_undef2( -; CHECK-NEXT: [[RET:%.*]] = and <3 x i8> [[X:%.*]], +; CHECK-NEXT: [[RET:%.*]] = and <3 x i8> [[X:%.*]], ; CHECK-NEXT: ret <3 x i8> [[RET]] ; %tmp0 = lshr <3 x i8> %x, diff --git a/test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll b/test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll index 45aa22aa808..9de0b337de2 100644 --- a/test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll +++ b/test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll @@ -171,7 +171,7 @@ define <3 x i32> @positive_sameconst_vec_undef1(<3 x i32> %x) { define <3 x i32> @positive_sameconst_vec_undef2(<3 x i32> %x) { ; CHECK-LABEL: @positive_sameconst_vec_undef2( -; CHECK-NEXT: [[RET:%.*]] = and <3 x i32> [[X:%.*]], +; CHECK-NEXT: [[RET:%.*]] = and <3 x i32> [[X:%.*]], ; CHECK-NEXT: ret <3 x i32> [[RET]] ; %tmp0 = shl <3 x i32> %x, diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index b48466e678d..5e6bed4e280 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -2876,7 +2876,7 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform(<2 x i32> %x) { define <2 x i1> @icmp_and_or_lshr_cst_vec_undef(<2 x i32> %x) { ; CHECK-LABEL: @icmp_and_or_lshr_cst_vec_undef( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] ; @@ -2920,7 +2920,7 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform_commute(<2 x i32> %xp) { define <2 x i1> @icmp_and_or_lshr_cst_vec_undef_commute(<2 x i32> %xp) { ; CHECK-LABEL: @icmp_and_or_lshr_cst_vec_undef_commute( ; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP:%.*]], -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] ; diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll index e49c381fcd1..89c16a0949e 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll @@ -103,7 +103,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T4]] -; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T7]] ; %t0 = add <8 x i32> %nbits, @@ -138,7 +138,7 @@ define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T4]] -; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T7]] ; %t0 = add <8 x i32> %nbits, diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll index 20f38deeb0d..8aef637c6a7 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll @@ -103,7 +103,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T4]] -; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T7]] ; %t0 = add <8 x i32> %nbits, @@ -138,7 +138,7 @@ define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T4]] -; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T7]] ; %t0 = add <8 x i32> %nbits, diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll index 562280391c5..61f25e6ca0b 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll @@ -83,7 +83,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = zext <8 x i32> %nbits to <8 x i64> @@ -110,7 +110,7 @@ define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = zext <8 x i32> %nbits to <8 x i64> diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll index aa644e6264e..077bb8296f3 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll @@ -93,7 +93,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T3]] -; CHECK-NEXT: [[T6:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T6:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T6]] ; %t0 = zext <8 x i32> %nbits to <8 x i64> @@ -124,7 +124,7 @@ define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T3]] -; CHECK-NEXT: [[T6:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T6:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T6]] ; %t0 = zext <8 x i32> %nbits to <8 x i64> diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll index f2aa2894e27..961ea5e4841 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll @@ -83,7 +83,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = zext <8 x i32> %nbits to <8 x i64> @@ -110,7 +110,7 @@ define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32> ; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = zext <8 x i32> %nbits to <8 x i64> diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll index 882117fe348..41a71aa98f4 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll @@ -82,7 +82,7 @@ define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits, @@ -109,7 +109,7 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits, diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll index e92875d7920..78713522914 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll @@ -82,7 +82,7 @@ define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits, @@ -109,7 +109,7 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]] -; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T5]] ; %t0 = add <8 x i32> %nbits, diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll index b8066cef2b4..c0959d9e1ac 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll @@ -62,7 +62,7 @@ define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T2]] -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T3]] ; %t0 = lshr <8 x i32> , %nbits @@ -81,7 +81,7 @@ define <8 x i32> @t1_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T2]] -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T3]] ; %t0 = lshr <8 x i32> , %nbits diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll index 20b322c0b64..5e0f0be2b1a 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll @@ -72,7 +72,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T3]] -; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T4]] ; %t0 = shl <8 x i32> , %nbits @@ -95,7 +95,7 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T3]] -; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T4]] ; %t0 = shl <8 x i32> , %nbits diff --git a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-e.ll b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-e.ll index 46f5b0c2f21..2e335f0083c 100644 --- a/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-e.ll +++ b/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-e.ll @@ -62,7 +62,7 @@ define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X]], [[T2]] -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T3]] ; %t0 = shl <8 x i32> %x, %nbits @@ -81,7 +81,7 @@ define <8 x i32> @t1_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]]) ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X]], [[T2]] -; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], +; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[TMP1]], ; CHECK-NEXT: ret <8 x i32> [[T3]] ; %t0 = shl <8 x i32> %x, %nbits diff --git a/test/Transforms/InstCombine/select-of-bittest.ll b/test/Transforms/InstCombine/select-of-bittest.ll index c85bcba82e9..d9bef00b2f7 100644 --- a/test/Transforms/InstCombine/select-of-bittest.ll +++ b/test/Transforms/InstCombine/select-of-bittest.ll @@ -82,7 +82,7 @@ define <2 x i32> @and_lshr_and_vec_v2(<2 x i32> %arg) { define <3 x i32> @and_lshr_and_vec_undef(<3 x i32> %arg) { ; CHECK-LABEL: @and_lshr_and_vec_undef( -; CHECK-NEXT: [[TMP1:%.*]] = and <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP1:%.*]] = and <3 x i32> [[ARG:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <3 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = zext <3 x i1> [[TMP2]] to <3 x i32> ; CHECK-NEXT: ret <3 x i32> [[TMP4]] @@ -91,7 +91,6 @@ define <3 x i32> @and_lshr_and_vec_undef(<3 x i32> %arg) { %tmp1 = icmp eq <3 x i32> %tmp, %tmp2 = lshr <3 x i32> %arg, %tmp3 = and <3 x i32> %tmp2, - ; The second element of %tmp4 is poison because it is (undef ? poison : undef). %tmp4 = select <3 x i1> %tmp1, <3 x i32> %tmp3, <3 x i32> ret <3 x i32> %tmp4 } @@ -223,7 +222,7 @@ define <2 x i32> @f_var0_vec(<2 x i32> %arg, <2 x i32> %arg1) { define <3 x i32> @f_var0_vec_undef(<3 x i32> %arg, <3 x i32> %arg1) { ; CHECK-LABEL: @f_var0_vec_undef( -; CHECK-NEXT: [[TMP1:%.*]] = or <3 x i32> [[ARG1:%.*]], +; CHECK-NEXT: [[TMP1:%.*]] = or <3 x i32> [[ARG1:%.*]], ; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[ARG:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = zext <3 x i1> [[TMP3]] to <3 x i32> @@ -233,7 +232,6 @@ define <3 x i32> @f_var0_vec_undef(<3 x i32> %arg, <3 x i32> %arg1) { %tmp2 = icmp eq <3 x i32> %tmp, %tmp3 = lshr <3 x i32> %arg, %tmp4 = and <3 x i32> %tmp3, - ; The second element of %tmp5 is poison because it is (undef ? poison : undef). %tmp5 = select <3 x i1> %tmp2, <3 x i32> %tmp4, <3 x i32> ret <3 x i32> %tmp5 } diff --git a/test/Transforms/InstCombine/shift-add-inseltpoison.ll b/test/Transforms/InstCombine/shift-add-inseltpoison.ll index 3232cdc49c0..e968f13c40b 100644 --- a/test/Transforms/InstCombine/shift-add-inseltpoison.ll +++ b/test/Transforms/InstCombine/shift-add-inseltpoison.ll @@ -40,7 +40,7 @@ define i32 @lshr_C1_add_A_C2_i32(i32 %A) { define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) { ; CHECK-LABEL: @shl_C1_add_A_C2_v4i32( ; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32> -; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> , [[B]] +; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> , [[B]] ; CHECK-NEXT: ret <4 x i32> [[D]] ; %B = zext <4 x i16> %A to <4 x i32> @@ -52,7 +52,7 @@ define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) { define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) { ; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32( ; CHECK-NEXT: [[B:%.*]] = and <4 x i32> [[A:%.*]], -; CHECK-NEXT: [[D:%.*]] = ashr <4 x i32> , [[B]] +; CHECK-NEXT: [[D:%.*]] = ashr <4 x i32> , [[B]] ; CHECK-NEXT: ret <4 x i32> [[D]] ; %B = and <4 x i32> %A, @@ -64,7 +64,7 @@ define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) { define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) { ; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32( ; CHECK-NEXT: [[B:%.*]] = and <4 x i32> [[A:%.*]], -; CHECK-NEXT: [[D:%.*]] = lshr <4 x i32> , [[B]] +; CHECK-NEXT: [[D:%.*]] = lshr <4 x i32> , [[B]] ; CHECK-NEXT: ret <4 x i32> [[D]] ; %B = and <4 x i32> %A, @@ -78,7 +78,7 @@ define <4 x i32> @shl_C1_add_A_C2_v4i32_splat(i16 %I) { ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0 ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[E:%.*]] = shl <4 x i32> , [[C]] +; CHECK-NEXT: [[E:%.*]] = shl <4 x i32> , [[C]] ; CHECK-NEXT: ret <4 x i32> [[E]] ; %A = zext i16 %I to i32 @@ -94,7 +94,7 @@ define <4 x i32> @ashr_C1_add_A_C2_v4i32_splat(i16 %I) { ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0 ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[E:%.*]] = ashr <4 x i32> , [[C]] +; CHECK-NEXT: [[E:%.*]] = ashr <4 x i32> , [[C]] ; CHECK-NEXT: ret <4 x i32> [[E]] ; %A = zext i16 %I to i32 @@ -110,7 +110,7 @@ define <4 x i32> @lshr_C1_add_A_C2_v4i32_splat(i16 %I) { ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0 ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[E:%.*]] = lshr <4 x i32> , [[C]] +; CHECK-NEXT: [[E:%.*]] = lshr <4 x i32> , [[C]] ; CHECK-NEXT: ret <4 x i32> [[E]] ; %A = zext i16 %I to i32 diff --git a/test/Transforms/InstCombine/shift-add.ll b/test/Transforms/InstCombine/shift-add.ll index eea8b7a074d..e227274f493 100644 --- a/test/Transforms/InstCombine/shift-add.ll +++ b/test/Transforms/InstCombine/shift-add.ll @@ -40,7 +40,7 @@ define i32 @lshr_C1_add_A_C2_i32(i32 %A) { define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) { ; CHECK-LABEL: @shl_C1_add_A_C2_v4i32( ; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32> -; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> , [[B]] +; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> , [[B]] ; CHECK-NEXT: ret <4 x i32> [[D]] ; %B = zext <4 x i16> %A to <4 x i32> @@ -52,7 +52,7 @@ define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) { define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) { ; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32( ; CHECK-NEXT: [[B:%.*]] = and <4 x i32> [[A:%.*]], -; CHECK-NEXT: [[D:%.*]] = ashr <4 x i32> , [[B]] +; CHECK-NEXT: [[D:%.*]] = ashr <4 x i32> , [[B]] ; CHECK-NEXT: ret <4 x i32> [[D]] ; %B = and <4 x i32> %A, @@ -64,7 +64,7 @@ define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) { define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) { ; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32( ; CHECK-NEXT: [[B:%.*]] = and <4 x i32> [[A:%.*]], -; CHECK-NEXT: [[D:%.*]] = lshr <4 x i32> , [[B]] +; CHECK-NEXT: [[D:%.*]] = lshr <4 x i32> , [[B]] ; CHECK-NEXT: ret <4 x i32> [[D]] ; %B = and <4 x i32> %A, @@ -78,7 +78,7 @@ define <4 x i32> @shl_C1_add_A_C2_v4i32_splat(i16 %I) { ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0 ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer -; CHECK-NEXT: [[E:%.*]] = shl <4 x i32> , [[C]] +; CHECK-NEXT: [[E:%.*]] = shl <4 x i32> , [[C]] ; CHECK-NEXT: ret <4 x i32> [[E]] ; %A = zext i16 %I to i32 @@ -94,7 +94,7 @@ define <4 x i32> @ashr_C1_add_A_C2_v4i32_splat(i16 %I) { ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0 ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer -; CHECK-NEXT: [[E:%.*]] = ashr <4 x i32> , [[C]] +; CHECK-NEXT: [[E:%.*]] = ashr <4 x i32> , [[C]] ; CHECK-NEXT: ret <4 x i32> [[E]] ; %A = zext i16 %I to i32 @@ -110,7 +110,7 @@ define <4 x i32> @lshr_C1_add_A_C2_v4i32_splat(i16 %I) { ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0 ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer -; CHECK-NEXT: [[E:%.*]] = lshr <4 x i32> , [[C]] +; CHECK-NEXT: [[E:%.*]] = lshr <4 x i32> , [[C]] ; CHECK-NEXT: ret <4 x i32> [[E]] ; %A = zext i16 %I to i32 diff --git a/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll b/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll index 54b862c8514..197e7cc0ac7 100644 --- a/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll +++ b/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll @@ -25,7 +25,7 @@ define <4 x i64> @insertelement() { define <4 x i64> @insertelement_undef() { ; CHECK-LABEL: @insertelement_undef( -; CHECK-NEXT: ret <4 x i64> poison +; CHECK-NEXT: ret <4 x i64> undef ; %vec1 = insertelement <4 x i64> poison, i64 -1, i32 0 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1 diff --git a/test/Transforms/InstSimplify/ConstProp/InsertElement.ll b/test/Transforms/InstSimplify/ConstProp/InsertElement.ll index 127c1692b5b..a9a27a5df01 100644 --- a/test/Transforms/InstSimplify/ConstProp/InsertElement.ll +++ b/test/Transforms/InstSimplify/ConstProp/InsertElement.ll @@ -25,7 +25,7 @@ define <4 x i64> @insertelement() { define <4 x i64> @insertelement_undef() { ; CHECK-LABEL: @insertelement_undef( -; CHECK-NEXT: ret <4 x i64> poison +; CHECK-NEXT: ret <4 x i64> undef ; %vec1 = insertelement <4 x i64> undef, i64 -1, i32 0 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1 diff --git a/test/Transforms/InstSimplify/ConstProp/cast.ll b/test/Transforms/InstSimplify/ConstProp/cast.ll index 1136151f715..adf5e4b68a1 100644 --- a/test/Transforms/InstSimplify/ConstProp/cast.ll +++ b/test/Transforms/InstSimplify/ConstProp/cast.ll @@ -5,7 +5,7 @@ define i8 @overflow_fptosi() { ; CHECK-LABEL: @overflow_fptosi( -; CHECK-NEXT: ret i8 poison +; CHECK-NEXT: ret i8 undef ; %i = fptosi double 1.56e+02 to i8 ret i8 %i @@ -13,7 +13,7 @@ define i8 @overflow_fptosi() { define i8 @overflow_fptoui() { ; CHECK-LABEL: @overflow_fptoui( -; CHECK-NEXT: ret i8 poison +; CHECK-NEXT: ret i8 undef ; %i = fptoui double 2.56e+02 to i8 ret i8 %i diff --git a/test/Transforms/InstSimplify/ConstProp/poison.ll b/test/Transforms/InstSimplify/ConstProp/poison.ll index f3fe29ff57b..ea34bb4699e 100644 --- a/test/Transforms/InstSimplify/ConstProp/poison.ll +++ b/test/Transforms/InstSimplify/ConstProp/poison.ll @@ -104,14 +104,14 @@ define void @vec_aggr_ops() { define void @other_ops(i8 %x) { ; CHECK-LABEL: @other_ops( -; CHECK-NEXT: call void (...) @use(i1 poison, i1 poison, i8 poison, i8 poison, i8* poison, i8* poison) +; CHECK-NEXT: call void (...) @use(i1 poison, i1 poison, i8 poison, i8 poison, i8* poison) ; CHECK-NEXT: ret void ; %i1 = icmp eq i8 poison, 1 %i2 = fcmp oeq float poison, 1.0 %i3 = select i1 poison, i8 1, i8 2 %i4 = select i1 true, i8 poison, i8 %x - call void (...) @use(i1 %i1, i1 %i2, i8 %i3, i8 %i4, i8* getelementptr (i8, i8* poison, i64 1), i8* getelementptr inbounds (i8, i8* undef, i64 1)) + call void (...) @use(i1 %i1, i1 %i2, i8 %i3, i8 %i4, i8* getelementptr (i8, i8* poison, i64 1)) ret void } diff --git a/test/Transforms/InstSimplify/ConstProp/shift.ll b/test/Transforms/InstSimplify/ConstProp/shift.ll index a7a60e56211..3e64513533f 100644 --- a/test/Transforms/InstSimplify/ConstProp/shift.ll +++ b/test/Transforms/InstSimplify/ConstProp/shift.ll @@ -3,15 +3,15 @@ ; CHECK-LABEL: shift_undef_64 define void @shift_undef_64(i64* %p) { %r1 = lshr i64 -1, 4294967296 ; 2^32 - ; CHECK: store i64 poison + ; CHECK: store i64 undef store i64 %r1, i64* %p %r2 = ashr i64 -1, 4294967297 ; 2^32 + 1 - ; CHECK: store i64 poison + ; CHECK: store i64 undef store i64 %r2, i64* %p %r3 = shl i64 -1, 4294967298 ; 2^32 + 2 - ; CHECK: store i64 poison + ; CHECK: store i64 undef store i64 %r3, i64* %p ret void @@ -20,15 +20,15 @@ define void @shift_undef_64(i64* %p) { ; CHECK-LABEL: shift_undef_65 define void @shift_undef_65(i65* %p) { %r1 = lshr i65 2, 18446744073709551617 - ; CHECK: store i65 poison + ; CHECK: store i65 undef store i65 %r1, i65* %p %r2 = ashr i65 4, 18446744073709551617 - ; CHECK: store i65 poison + ; CHECK: store i65 undef store i65 %r2, i65* %p %r3 = shl i65 1, 18446744073709551617 - ; CHECK: store i65 poison + ; CHECK: store i65 undef store i65 %r3, i65* %p ret void @@ -37,15 +37,15 @@ define void @shift_undef_65(i65* %p) { ; CHECK-LABEL: shift_undef_256 define void @shift_undef_256(i256* %p) { %r1 = lshr i256 2, 18446744073709551617 - ; CHECK: store i256 poison + ; CHECK: store i256 undef store i256 %r1, i256* %p %r2 = ashr i256 4, 18446744073709551618 - ; CHECK: store i256 poison + ; CHECK: store i256 undef store i256 %r2, i256* %p %r3 = shl i256 1, 18446744073709551619 - ; CHECK: store i256 poison + ; CHECK: store i256 undef store i256 %r3, i256* %p ret void @@ -54,15 +54,15 @@ define void @shift_undef_256(i256* %p) { ; CHECK-LABEL: shift_undef_511 define void @shift_undef_511(i511* %p) { %r1 = lshr i511 -1, 1208925819614629174706276 ; 2^80 + 100 - ; CHECK: store i511 poison + ; CHECK: store i511 undef store i511 %r1, i511* %p %r2 = ashr i511 -2, 1208925819614629174706200 - ; CHECK: store i511 poison + ; CHECK: store i511 undef store i511 %r2, i511* %p %r3 = shl i511 -3, 1208925819614629174706180 - ; CHECK: store i511 poison + ; CHECK: store i511 undef store i511 %r3, i511* %p ret void diff --git a/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll b/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll index 6ce03dd2e0f..2762291d795 100644 --- a/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll +++ b/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll @@ -5,7 +5,7 @@ define <3 x i8> @shl() { ; CHECK-LABEL: @shl( -; CHECK-NEXT: ret <3 x i8> +; CHECK-NEXT: ret <3 x i8> ; %c = shl <3 x i8> undef, ret <3 x i8> %c diff --git a/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll b/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll index 99cc2527d12..5d0f484bc3f 100644 --- a/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll +++ b/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll @@ -5,7 +5,7 @@ define <3 x i8> @shl() { ; CHECK-LABEL: @shl( -; CHECK-NEXT: ret <3 x i8> +; CHECK-NEXT: ret <3 x i8> ; %c = shl <3 x i8> undef, ret <3 x i8> %c diff --git a/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll b/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll index 9689887be69..ee19e617748 100644 --- a/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll +++ b/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll @@ -75,7 +75,7 @@ define @fmul() { define @udiv() { ; CHECK-LABEL: @udiv( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = udiv undef, undef ret %r @@ -83,7 +83,7 @@ define @udiv() { define @udiv_splat_zero() { ; CHECK-LABEL: @udiv_splat_zero( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = udiv zeroinitializer, zeroinitializer ret %r @@ -91,7 +91,7 @@ define @udiv_splat_zero() { define @sdiv() { ; CHECK-LABEL: @sdiv( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = sdiv undef, undef ret %r @@ -107,7 +107,7 @@ define @fdiv() { define @urem() { ; CHECK-LABEL: @urem( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = urem undef, undef ret %r @@ -115,7 +115,7 @@ define @urem() { define @srem() { ; CHECK-LABEL: @srem( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = srem undef, undef ret %r @@ -135,7 +135,7 @@ define @frem() { define @shl() { ; CHECK-LABEL: @shl( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = shl undef, undef ret %r @@ -143,7 +143,7 @@ define @shl() { define @lshr() { ; CHECK-LABEL: @lshr( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = lshr undef, undef ret %r @@ -151,7 +151,7 @@ define @lshr() { define @ashr() { ; CHECK-LABEL: @ashr( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = ashr undef, undef ret %r diff --git a/test/Transforms/InstSimplify/ConstProp/vscale.ll b/test/Transforms/InstSimplify/ConstProp/vscale.ll index 048e8840ffd..66e4c93e196 100644 --- a/test/Transforms/InstSimplify/ConstProp/vscale.ll +++ b/test/Transforms/InstSimplify/ConstProp/vscale.ll @@ -75,7 +75,7 @@ define @fmul() { define @udiv() { ; CHECK-LABEL: @udiv( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = udiv undef, undef ret %r @@ -83,7 +83,7 @@ define @udiv() { define @udiv_splat_zero() { ; CHECK-LABEL: @udiv_splat_zero( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = udiv zeroinitializer, zeroinitializer ret %r @@ -91,7 +91,7 @@ define @udiv_splat_zero() { define @sdiv() { ; CHECK-LABEL: @sdiv( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = sdiv undef, undef ret %r @@ -107,7 +107,7 @@ define @fdiv() { define @urem() { ; CHECK-LABEL: @urem( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = urem undef, undef ret %r @@ -115,7 +115,7 @@ define @urem() { define @srem() { ; CHECK-LABEL: @srem( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = srem undef, undef ret %r @@ -135,7 +135,7 @@ define @frem() { define @shl() { ; CHECK-LABEL: @shl( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = shl undef, undef ret %r @@ -143,7 +143,7 @@ define @shl() { define @lshr() { ; CHECK-LABEL: @lshr( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = lshr undef, undef ret %r @@ -151,7 +151,7 @@ define @lshr() { define @ashr() { ; CHECK-LABEL: @ashr( -; CHECK-NEXT: ret poison +; CHECK-NEXT: ret undef ; %r = ashr undef, undef ret %r diff --git a/test/Transforms/InstSimplify/div.ll b/test/Transforms/InstSimplify/div.ll index 7c8efc27d3a..5a3e6e8f7da 100644 --- a/test/Transforms/InstSimplify/div.ll +++ b/test/Transforms/InstSimplify/div.ll @@ -25,11 +25,11 @@ define <2 x i32> @zero_dividend_vector_undef_elt(<2 x i32> %A) { ret <2 x i32> %B } -; Division-by-zero is poison. UB in any vector lane means the whole op is poison. +; Division-by-zero is undef. UB in any vector lane means the whole op is undef. define <2 x i8> @sdiv_zero_elt_vec_constfold(<2 x i8> %x) { ; CHECK-LABEL: @sdiv_zero_elt_vec_constfold( -; CHECK-NEXT: ret <2 x i8> poison +; CHECK-NEXT: ret <2 x i8> undef ; %div = sdiv <2 x i8> , ret <2 x i8> %div @@ -37,7 +37,7 @@ define <2 x i8> @sdiv_zero_elt_vec_constfold(<2 x i8> %x) { define <2 x i8> @udiv_zero_elt_vec_constfold(<2 x i8> %x) { ; CHECK-LABEL: @udiv_zero_elt_vec_constfold( -; CHECK-NEXT: ret <2 x i8> poison +; CHECK-NEXT: ret <2 x i8> undef ; %div = udiv <2 x i8> , ret <2 x i8> %div @@ -193,37 +193,4 @@ define i32 @div1() { ret i32 %urem } -define i8 @sdiv_minusone_divisor() { -; CHECK-LABEL: @sdiv_minusone_divisor( -; CHECK-NEXT: ret i8 poison -; - %v = sdiv i8 -128, -1 - ret i8 %v -} - -define i32 @poison(i32 %x) { -; CHECK-LABEL: @poison( -; CHECK-NEXT: ret i32 poison -; - %v = udiv i32 %x, poison - ret i32 %v -} - -; TODO: this should be poison -define i32 @poison2(i32 %x) { -; CHECK-LABEL: @poison2( -; CHECK-NEXT: ret i32 0 -; - %v = udiv i32 poison, %x - ret i32 %v -} - -define <2 x i32> @poison3(<2 x i32> %x) { -; CHECK-LABEL: @poison3( -; CHECK-NEXT: ret <2 x i32> poison -; - %v = udiv <2 x i32> %x, - ret <2 x i32> %v -} - !0 = !{i32 0, i32 3} diff --git a/test/Transforms/InstSimplify/rem.ll b/test/Transforms/InstSimplify/rem.ll index 6aaeb5c70d0..6ccb6474ce4 100644 --- a/test/Transforms/InstSimplify/rem.ll +++ b/test/Transforms/InstSimplify/rem.ll @@ -25,11 +25,11 @@ define <2 x i32> @zero_dividend_vector_undef_elt(<2 x i32> %A) { ret <2 x i32> %B } -; Division-by-zero is poison. UB in any vector lane means the whole op is poison. +; Division-by-zero is undef. UB in any vector lane means the whole op is undef. define <2 x i8> @srem_zero_elt_vec_constfold(<2 x i8> %x) { ; CHECK-LABEL: @srem_zero_elt_vec_constfold( -; CHECK-NEXT: ret <2 x i8> poison +; CHECK-NEXT: ret <2 x i8> undef ; %rem = srem <2 x i8> , ret <2 x i8> %rem @@ -37,7 +37,7 @@ define <2 x i8> @srem_zero_elt_vec_constfold(<2 x i8> %x) { define <2 x i8> @urem_zero_elt_vec_constfold(<2 x i8> %x) { ; CHECK-LABEL: @urem_zero_elt_vec_constfold( -; CHECK-NEXT: ret <2 x i8> poison +; CHECK-NEXT: ret <2 x i8> undef ; %rem = urem <2 x i8> , ret <2 x i8> %rem @@ -325,28 +325,3 @@ define <2 x i32> @srem_with_sext_bool_divisor_vec(<2 x i1> %x, <2 x i32> %y) { ret <2 x i32> %r } -define i8 @srem_minusone_divisor() { -; CHECK-LABEL: @srem_minusone_divisor( -; CHECK-NEXT: ret i8 poison -; - %v = srem i8 -128, -1 - ret i8 %v -} - -define i32 @poison(i32 %x) { -; CHECK-LABEL: @poison( -; CHECK-NEXT: ret i32 poison -; - %v = urem i32 %x, poison - ret i32 %v -} - -; TODO: this should be poison - -define i32 @poison2(i32 %x) { -; CHECK-LABEL: @poison2( -; CHECK-NEXT: ret i32 0 -; - %v = urem i32 poison, %x - ret i32 %v -} diff --git a/test/Transforms/InstSimplify/undef.ll b/test/Transforms/InstSimplify/undef.ll index d09dc43da09..fe1f412d3d3 100644 --- a/test/Transforms/InstSimplify/undef.ll +++ b/test/Transforms/InstSimplify/undef.ll @@ -1,9 +1,8 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -instsimplify -S < %s | FileCheck %s define i64 @test0() { ; CHECK-LABEL: @test0( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = mul i64 undef, undef ret i64 %r @@ -11,7 +10,7 @@ define i64 @test0() { define i64 @test1() { ; CHECK-LABEL: @test1( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = mul i64 3, undef ret i64 %r @@ -19,7 +18,7 @@ define i64 @test1() { define i64 @test2() { ; CHECK-LABEL: @test2( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = mul i64 undef, 3 ret i64 %r @@ -27,7 +26,7 @@ define i64 @test2() { define i64 @test3() { ; CHECK-LABEL: @test3( -; CHECK-NEXT: ret i64 0 +; CHECK: ret i64 0 ; %r = mul i64 undef, 6 ret i64 %r @@ -35,7 +34,7 @@ define i64 @test3() { define i64 @test4() { ; CHECK-LABEL: @test4( -; CHECK-NEXT: ret i64 0 +; CHECK: ret i64 0 ; %r = mul i64 6, undef ret i64 %r @@ -43,7 +42,7 @@ define i64 @test4() { define i64 @test5() { ; CHECK-LABEL: @test5( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = and i64 undef, undef ret i64 %r @@ -51,7 +50,7 @@ define i64 @test5() { define i64 @test6() { ; CHECK-LABEL: @test6( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = or i64 undef, undef ret i64 %r @@ -59,7 +58,7 @@ define i64 @test6() { define i64 @test7() { ; CHECK-LABEL: @test7( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = udiv i64 undef, 1 ret i64 %r @@ -67,7 +66,7 @@ define i64 @test7() { define i64 @test8() { ; CHECK-LABEL: @test8( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = sdiv i64 undef, 1 ret i64 %r @@ -75,7 +74,7 @@ define i64 @test8() { define i64 @test9() { ; CHECK-LABEL: @test9( -; CHECK-NEXT: ret i64 0 +; CHECK: ret i64 0 ; %r = urem i64 undef, 1 ret i64 %r @@ -83,7 +82,7 @@ define i64 @test9() { define i64 @test10() { ; CHECK-LABEL: @test10( -; CHECK-NEXT: ret i64 0 +; CHECK: ret i64 0 ; %r = srem i64 undef, 1 ret i64 %r @@ -91,7 +90,7 @@ define i64 @test10() { define i64 @test11() { ; CHECK-LABEL: @test11( -; CHECK-NEXT: ret i64 poison +; CHECK: ret i64 undef ; %r = shl i64 undef, undef ret i64 %r @@ -99,7 +98,7 @@ define i64 @test11() { define i64 @test11b(i64 %a) { ; CHECK-LABEL: @test11b( -; CHECK-NEXT: ret i64 poison +; CHECK: ret i64 poison ; %r = shl i64 %a, undef ret i64 %r @@ -107,7 +106,7 @@ define i64 @test11b(i64 %a) { define i64 @test12() { ; CHECK-LABEL: @test12( -; CHECK-NEXT: ret i64 poison +; CHECK: ret i64 undef ; %r = ashr i64 undef, undef ret i64 %r @@ -115,7 +114,7 @@ define i64 @test12() { define i64 @test12b(i64 %a) { ; CHECK-LABEL: @test12b( -; CHECK-NEXT: ret i64 poison +; CHECK: ret i64 poison ; %r = ashr i64 %a, undef ret i64 %r @@ -123,7 +122,7 @@ define i64 @test12b(i64 %a) { define i64 @test13() { ; CHECK-LABEL: @test13( -; CHECK-NEXT: ret i64 poison +; CHECK: ret i64 undef ; %r = lshr i64 undef, undef ret i64 %r @@ -131,7 +130,7 @@ define i64 @test13() { define i64 @test13b(i64 %a) { ; CHECK-LABEL: @test13b( -; CHECK-NEXT: ret i64 poison +; CHECK: ret i64 poison ; %r = lshr i64 %a, undef ret i64 %r @@ -139,7 +138,7 @@ define i64 @test13b(i64 %a) { define i1 @test14() { ; CHECK-LABEL: @test14( -; CHECK-NEXT: ret i1 undef +; CHECK: ret i1 undef ; %r = icmp slt i64 undef, undef ret i1 %r @@ -147,7 +146,7 @@ define i1 @test14() { define i1 @test15() { ; CHECK-LABEL: @test15( -; CHECK-NEXT: ret i1 undef +; CHECK: ret i1 undef ; %r = icmp ult i64 undef, undef ret i1 %r @@ -155,7 +154,7 @@ define i1 @test15() { define i64 @test16(i64 %a) { ; CHECK-LABEL: @test16( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = select i1 undef, i64 %a, i64 undef ret i64 %r @@ -163,7 +162,7 @@ define i64 @test16(i64 %a) { define i64 @test17(i64 %a) { ; CHECK-LABEL: @test17( -; CHECK-NEXT: ret i64 undef +; CHECK: ret i64 undef ; %r = select i1 undef, i64 undef, i64 %a ret i64 %r @@ -171,7 +170,7 @@ define i64 @test17(i64 %a) { define i64 @test18(i64 %a) { ; CHECK-LABEL: @test18( -; CHECK-NEXT: [[R:%.*]] = call i64 undef(i64 [[A:%.*]]) +; CHECK: [[R:%.*]] = call i64 undef(i64 %a) ; CHECK-NEXT: ret i64 poison ; %r = call i64 (i64) undef(i64 %a) @@ -180,7 +179,7 @@ define i64 @test18(i64 %a) { define <4 x i8> @test19(<4 x i8> %a) { ; CHECK-LABEL: @test19( -; CHECK-NEXT: ret <4 x i8> poison +; CHECK: ret <4 x i8> poison ; %b = shl <4 x i8> %a, ret <4 x i8> %b @@ -188,7 +187,7 @@ define <4 x i8> @test19(<4 x i8> %a) { define i32 @test20(i32 %a) { ; CHECK-LABEL: @test20( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 poison ; %b = udiv i32 %a, 0 ret i32 %b @@ -204,7 +203,7 @@ define <2 x i32> @test20vec(<2 x i32> %a) { define i32 @test21(i32 %a) { ; CHECK-LABEL: @test21( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 poison ; %b = sdiv i32 %a, 0 ret i32 %b @@ -220,7 +219,7 @@ define <2 x i32> @test21vec(<2 x i32> %a) { define i32 @test22(i32 %a) { ; CHECK-LABEL: @test22( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = ashr exact i32 undef, %a ret i32 %b @@ -228,7 +227,7 @@ define i32 @test22(i32 %a) { define i32 @test23(i32 %a) { ; CHECK-LABEL: @test23( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = lshr exact i32 undef, %a ret i32 %b @@ -236,7 +235,7 @@ define i32 @test23(i32 %a) { define i32 @test24() { ; CHECK-LABEL: @test24( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 undef ; %b = udiv i32 undef, 0 ret i32 %b @@ -244,7 +243,7 @@ define i32 @test24() { define i32 @test25() { ; CHECK-LABEL: @test25( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 undef ; %b = lshr i32 0, undef ret i32 %b @@ -252,7 +251,7 @@ define i32 @test25() { define i32 @test26() { ; CHECK-LABEL: @test26( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 undef ; %b = ashr i32 0, undef ret i32 %b @@ -260,7 +259,7 @@ define i32 @test26() { define i32 @test27() { ; CHECK-LABEL: @test27( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 undef ; %b = shl i32 0, undef ret i32 %b @@ -268,7 +267,7 @@ define i32 @test27() { define i32 @test28(i32 %a) { ; CHECK-LABEL: @test28( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = shl nsw i32 undef, %a ret i32 %b @@ -276,7 +275,7 @@ define i32 @test28(i32 %a) { define i32 @test29(i32 %a) { ; CHECK-LABEL: @test29( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = shl nuw i32 undef, %a ret i32 %b @@ -284,7 +283,7 @@ define i32 @test29(i32 %a) { define i32 @test30(i32 %a) { ; CHECK-LABEL: @test30( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = shl nsw nuw i32 undef, %a ret i32 %b @@ -292,7 +291,7 @@ define i32 @test30(i32 %a) { define i32 @test31(i32 %a) { ; CHECK-LABEL: @test31( -; CHECK-NEXT: ret i32 0 +; CHECK: ret i32 0 ; %b = shl i32 undef, %a ret i32 %b @@ -300,7 +299,7 @@ define i32 @test31(i32 %a) { define i32 @test32(i32 %a) { ; CHECK-LABEL: @test32( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = shl i32 undef, 0 ret i32 %b @@ -308,7 +307,7 @@ define i32 @test32(i32 %a) { define i32 @test33(i32 %a) { ; CHECK-LABEL: @test33( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = ashr i32 undef, 0 ret i32 %b @@ -316,7 +315,7 @@ define i32 @test33(i32 %a) { define i32 @test34(i32 %a) { ; CHECK-LABEL: @test34( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = lshr i32 undef, 0 ret i32 %b @@ -324,7 +323,7 @@ define i32 @test34(i32 %a) { define i32 @test35(<4 x i32> %V) { ; CHECK-LABEL: @test35( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 poison ; %b = extractelement <4 x i32> %V, i32 4 ret i32 %b @@ -332,7 +331,7 @@ define i32 @test35(<4 x i32> %V) { define i32 @test36(i32 %V) { ; CHECK-LABEL: @test36( -; CHECK-NEXT: ret i32 undef +; CHECK: ret i32 undef ; %b = extractelement <4 x i32> undef, i32 %V ret i32 %b @@ -340,7 +339,7 @@ define i32 @test36(i32 %V) { define i32 @test37() { ; CHECK-LABEL: @test37( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 undef ; %b = udiv i32 undef, undef ret i32 %b @@ -348,7 +347,7 @@ define i32 @test37() { define i32 @test38(i32 %a) { ; CHECK-LABEL: @test38( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 poison ; %b = udiv i32 %a, undef ret i32 %b @@ -356,7 +355,7 @@ define i32 @test38(i32 %a) { define i32 @test39() { ; CHECK-LABEL: @test39( -; CHECK-NEXT: ret i32 poison +; CHECK: ret i32 undef ; %b = udiv i32 0, undef ret i32 %b diff --git a/test/Transforms/SROA/phi-gep.ll b/test/Transforms/SROA/phi-gep.ll index 915ae546bed..6bf2a771865 100644 --- a/test/Transforms/SROA/phi-gep.ll +++ b/test/Transforms/SROA/phi-gep.ll @@ -348,7 +348,7 @@ define void @test_sroa_gep_phi_select_same_block() { ; CHECK-NEXT: [[PHI:%.*]] = phi %pair* [ [[ALLOCA]], [[ENTRY:%.*]] ], [ [[SELECT:%.*]], [[WHILE_BODY]] ] ; CHECK-NEXT: [[SELECT]] = select i1 undef, %pair* [[PHI]], %pair* undef ; CHECK-NEXT: [[PHI_SROA_GEP:%.*]] = getelementptr inbounds [[PAIR]], %pair* [[PHI]], i64 1 -; CHECK-NEXT: [[SELECT_SROA_SEL:%.*]] = select i1 undef, %pair* [[PHI_SROA_GEP]], %pair* poison +; CHECK-NEXT: [[SELECT_SROA_SEL:%.*]] = select i1 undef, %pair* [[PHI_SROA_GEP]], %pair* undef ; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[WHILE_BODY]] ; CHECK: exit: ; CHECK-NEXT: unreachable diff --git a/test/Transforms/SROA/select-gep.ll b/test/Transforms/SROA/select-gep.ll index f69cfeb410b..93cb3420d0a 100644 --- a/test/Transforms/SROA/select-gep.ll +++ b/test/Transforms/SROA/select-gep.ll @@ -83,7 +83,7 @@ define i32 @test_sroa_select_gep_undef(i1 %cond) { ; CHECK-LABEL: @test_sroa_select_gep_undef( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i32, align 4 -; CHECK-NEXT: [[SELECT_SROA_SEL:%.*]] = select i1 [[COND:%.*]], i32* [[A_SROA_0]], i32* poison +; CHECK-NEXT: [[SELECT_SROA_SEL:%.*]] = select i1 [[COND:%.*]], i32* [[A_SROA_0]], i32* undef ; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[SELECT_SROA_SEL]], align 4 ; CHECK-NEXT: ret i32 [[LOAD]] ; diff --git a/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll b/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll index 8a6b1e98c96..b9d82e9f81d 100644 --- a/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll +++ b/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll @@ -128,7 +128,7 @@ define <2 x i64> @ins1_ins1_sdiv(i64 %x, i64 %y) { define <2 x i64> @ins1_ins1_udiv(i64 %x, i64 %y) { ; CHECK-LABEL: @ins1_ins1_udiv( ; CHECK-NEXT: [[R_SCALAR:%.*]] = udiv i64 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[R]] ; %i0 = insertelement <2 x i64> , i64 %x, i32 1 @@ -143,7 +143,7 @@ define <2 x i64> @ins1_ins1_udiv(i64 %x, i64 %y) { define <2 x i64> @ins1_ins1_urem(i64 %x, i64 %y) { ; CHECK-LABEL: @ins1_ins1_urem( ; CHECK-NEXT: [[R_SCALAR:%.*]] = urem i64 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[R]] ; %i0 = insertelement <2 x i64> , i64 %x, i64 1 diff --git a/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll b/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll index 0637b500568..a400e8f4290 100644 --- a/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll +++ b/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll @@ -131,7 +131,7 @@ define <16 x i8> @mul_constant_multiuse(i8 %a0, <16 x i8> %a1) { define <2 x i64> @shl_constant_op0(i64 %x) { ; CHECK-LABEL: @shl_constant_op0( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = shl i64 2, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -142,7 +142,7 @@ define <2 x i64> @shl_constant_op0(i64 %x) { define <2 x i64> @shl_constant_op0_not_undef_lane(i64 %x) { ; CHECK-LABEL: @shl_constant_op0_not_undef_lane( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = shl i64 2, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -189,7 +189,7 @@ define <4 x i32> @shl_constant_op0_multiuse(i32 %a0, <4 x i32> %a1) { define <2 x i64> @shl_constant_op1(i64 %x) { ; CHECK-LABEL: @shl_constant_op1( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = shl nuw i64 [[X:%.*]], 5 -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -224,7 +224,7 @@ define <2 x i64> @shl_constant_op1_load(i64* %p) { define <2 x i64> @ashr_constant_op0(i64 %x) { ; CHECK-LABEL: @ashr_constant_op0( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = ashr exact i64 2, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -235,7 +235,7 @@ define <2 x i64> @ashr_constant_op0(i64 %x) { define <2 x i64> @ashr_constant_op0_not_undef_lane(i64 %x) { ; CHECK-LABEL: @ashr_constant_op0_not_undef_lane( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = ashr exact i64 2, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -246,7 +246,7 @@ define <2 x i64> @ashr_constant_op0_not_undef_lane(i64 %x) { define <2 x i64> @ashr_constant_op1(i64 %x) { ; CHECK-LABEL: @ashr_constant_op1( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = ashr i64 [[X:%.*]], 5 -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -268,7 +268,7 @@ define <2 x i64> @ashr_constant_op1_not_undef_lane(i64 %x) { define <2 x i64> @lshr_constant_op0(i64 %x) { ; CHECK-LABEL: @lshr_constant_op0( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = lshr i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -279,7 +279,7 @@ define <2 x i64> @lshr_constant_op0(i64 %x) { define <2 x i64> @lshr_constant_op0_not_undef_lane(i64 %x) { ; CHECK-LABEL: @lshr_constant_op0_not_undef_lane( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = lshr i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -290,7 +290,7 @@ define <2 x i64> @lshr_constant_op0_not_undef_lane(i64 %x) { define <2 x i64> @lshr_constant_op1(i64 %x) { ; CHECK-LABEL: @lshr_constant_op1( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = lshr exact i64 [[X:%.*]], 2 -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -312,7 +312,7 @@ define <2 x i64> @lshr_constant_op1_not_undef_lane(i64 %x) { define <2 x i64> @urem_constant_op0(i64 %x) { ; CHECK-LABEL: @urem_constant_op0( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = urem i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -323,7 +323,7 @@ define <2 x i64> @urem_constant_op0(i64 %x) { define <2 x i64> @urem_constant_op0_not_undef_lane(i64 %x) { ; CHECK-LABEL: @urem_constant_op0_not_undef_lane( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = urem i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -334,7 +334,7 @@ define <2 x i64> @urem_constant_op0_not_undef_lane(i64 %x) { define <2 x i64> @urem_constant_op1(i64 %x) { ; CHECK-LABEL: @urem_constant_op1( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = urem i64 [[X:%.*]], 2 -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -356,7 +356,7 @@ define <2 x i64> @urem_constant_op1_not_undef_lane(i64 %x) { define <2 x i64> @srem_constant_op0(i64 %x) { ; CHECK-LABEL: @srem_constant_op0( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = srem i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -367,7 +367,7 @@ define <2 x i64> @srem_constant_op0(i64 %x) { define <2 x i64> @srem_constant_op0_not_undef_lane(i64 %x) { ; CHECK-LABEL: @srem_constant_op0_not_undef_lane( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = srem i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -378,7 +378,7 @@ define <2 x i64> @srem_constant_op0_not_undef_lane(i64 %x) { define <2 x i64> @srem_constant_op1(i64 %x) { ; CHECK-LABEL: @srem_constant_op1( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = srem i64 [[X:%.*]], 2 -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -400,7 +400,7 @@ define <2 x i64> @srem_constant_op1_not_undef_lane(i64 %x) { define <2 x i64> @udiv_constant_op0(i64 %x) { ; CHECK-LABEL: @udiv_constant_op0( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = udiv exact i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -411,7 +411,7 @@ define <2 x i64> @udiv_constant_op0(i64 %x) { define <2 x i64> @udiv_constant_op0_not_undef_lane(i64 %x) { ; CHECK-LABEL: @udiv_constant_op0_not_undef_lane( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = udiv exact i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -422,7 +422,7 @@ define <2 x i64> @udiv_constant_op0_not_undef_lane(i64 %x) { define <2 x i64> @udiv_constant_op1(i64 %x) { ; CHECK-LABEL: @udiv_constant_op1( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = udiv i64 [[X:%.*]], 2 -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -444,7 +444,7 @@ define <2 x i64> @udiv_constant_op1_not_undef_lane(i64 %x) { define <2 x i64> @sdiv_constant_op0(i64 %x) { ; CHECK-LABEL: @sdiv_constant_op0( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = sdiv i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -455,7 +455,7 @@ define <2 x i64> @sdiv_constant_op0(i64 %x) { define <2 x i64> @sdiv_constant_op0_not_undef_lane(i64 %x) { ; CHECK-LABEL: @sdiv_constant_op0_not_undef_lane( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = sdiv i64 5, [[X:%.*]] -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> undef, i64 [[BO_SCALAR]], i64 0 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 0 @@ -466,7 +466,7 @@ define <2 x i64> @sdiv_constant_op0_not_undef_lane(i64 %x) { define <2 x i64> @sdiv_constant_op1(i64 %x) { ; CHECK-LABEL: @sdiv_constant_op1( ; CHECK-NEXT: [[BO_SCALAR:%.*]] = sdiv exact i64 [[X:%.*]], 2 -; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 +; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x i64> , i64 [[BO_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[BO]] ; %ins = insertelement <2 x i64> undef, i64 %x, i32 1 diff --git a/test/Transforms/VectorCombine/X86/insert-binop.ll b/test/Transforms/VectorCombine/X86/insert-binop.ll index 4fd33cc7ef2..abebf4d809a 100644 --- a/test/Transforms/VectorCombine/X86/insert-binop.ll +++ b/test/Transforms/VectorCombine/X86/insert-binop.ll @@ -53,7 +53,7 @@ define <2 x i64> @ins1_ins1_iterate(i64 %w, i64 %x, i64 %y, i64 %z) { ; CHECK-NEXT: [[S0_SCALAR:%.*]] = sub i64 [[W:%.*]], [[X:%.*]] ; CHECK-NEXT: [[S1_SCALAR:%.*]] = or i64 [[S0_SCALAR]], [[Y:%.*]] ; CHECK-NEXT: [[S2_SCALAR:%.*]] = shl i64 [[Z:%.*]], [[S1_SCALAR]] -; CHECK-NEXT: [[S2:%.*]] = insertelement <2 x i64> poison, i64 [[S2_SCALAR]], i64 1 +; CHECK-NEXT: [[S2:%.*]] = insertelement <2 x i64> undef, i64 [[S2_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[S2]] ; %i0 = insertelement <2 x i64> undef, i64 %w, i64 1 @@ -128,7 +128,7 @@ define <2 x i64> @ins1_ins1_sdiv(i64 %x, i64 %y) { define <2 x i64> @ins1_ins1_udiv(i64 %x, i64 %y) { ; CHECK-LABEL: @ins1_ins1_udiv( ; CHECK-NEXT: [[R_SCALAR:%.*]] = udiv i64 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[R]] ; %i0 = insertelement <2 x i64> , i64 %x, i32 1 @@ -143,7 +143,7 @@ define <2 x i64> @ins1_ins1_udiv(i64 %x, i64 %y) { define <2 x i64> @ins1_ins1_urem(i64 %x, i64 %y) { ; CHECK-LABEL: @ins1_ins1_urem( ; CHECK-NEXT: [[R_SCALAR:%.*]] = urem i64 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i64> , i64 [[R_SCALAR]], i64 1 ; CHECK-NEXT: ret <2 x i64> [[R]] ; %i0 = insertelement <2 x i64> , i64 %x, i64 1 diff --git a/unittests/IR/ConstantsTest.cpp b/unittests/IR/ConstantsTest.cpp index 9eabc7c5563..96d3672647e 100644 --- a/unittests/IR/ConstantsTest.cpp +++ b/unittests/IR/ConstantsTest.cpp @@ -27,7 +27,7 @@ TEST(ConstantsTest, Integer_i1) { Constant* Zero = ConstantInt::get(Int1, 0); Constant* NegOne = ConstantInt::get(Int1, static_cast(-1), true); EXPECT_EQ(NegOne, ConstantInt::getSigned(Int1, -1)); - Constant* Poison = PoisonValue::get(Int1); + Constant* Undef = UndefValue::get(Int1); // Input: @b = constant i1 add(i1 1 , i1 1) // Output: @b = constant i1 false @@ -53,21 +53,21 @@ TEST(ConstantsTest, Integer_i1) { // @g = constant i1 false EXPECT_EQ(Zero, ConstantExpr::getSub(One, One)); - // @h = constant i1 shl(i1 1 , i1 1) ; poison - // @h = constant i1 poison - EXPECT_EQ(Poison, ConstantExpr::getShl(One, One)); + // @h = constant i1 shl(i1 1 , i1 1) ; undefined + // @h = constant i1 undef + EXPECT_EQ(Undef, ConstantExpr::getShl(One, One)); // @i = constant i1 shl(i1 1 , i1 0) // @i = constant i1 true EXPECT_EQ(One, ConstantExpr::getShl(One, Zero)); - // @j = constant i1 lshr(i1 1, i1 1) ; poison - // @j = constant i1 poison - EXPECT_EQ(Poison, ConstantExpr::getLShr(One, One)); + // @j = constant i1 lshr(i1 1, i1 1) ; undefined + // @j = constant i1 undef + EXPECT_EQ(Undef, ConstantExpr::getLShr(One, One)); - // @m = constant i1 ashr(i1 1, i1 1) ; poison - // @m = constant i1 poison - EXPECT_EQ(Poison, ConstantExpr::getAShr(One, One)); + // @m = constant i1 ashr(i1 1, i1 1) ; undefined + // @m = constant i1 undef + EXPECT_EQ(Undef, ConstantExpr::getAShr(One, One)); // @n = constant i1 mul(i1 -1, i1 1) // @n = constant i1 true @@ -218,6 +218,7 @@ TEST(ConstantsTest, AsInstructionsTest) { Constant *Elt = ConstantInt::get(Int16Ty, 2015); Constant *Poison16 = PoisonValue::get(Int16Ty); Constant *Undef64 = UndefValue::get(Int64Ty); + Constant *UndefV16 = UndefValue::get(P6->getType()); Constant *PoisonV16 = PoisonValue::get(P6->getType()); #define P0STR "ptrtoint (i32** @dummy to i32)" @@ -294,8 +295,8 @@ TEST(ConstantsTest, AsInstructionsTest) { EXPECT_EQ(Elt, ConstantExpr::getExtractElement( ConstantExpr::getInsertElement(P6, Elt, One), One)); - EXPECT_EQ(PoisonV16, ConstantExpr::getInsertElement(P6, Elt, Two)); - EXPECT_EQ(PoisonV16, ConstantExpr::getInsertElement(P6, Elt, Big)); + EXPECT_EQ(UndefV16, ConstantExpr::getInsertElement(P6, Elt, Two)); + EXPECT_EQ(UndefV16, ConstantExpr::getInsertElement(P6, Elt, Big)); EXPECT_EQ(PoisonV16, ConstantExpr::getInsertElement(P6, Elt, Undef64)); }