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[PowerPC] Legalize saturating vector add/sub
These intrinsics and the corresponding ISD nodes were recently added. PPC has instructions that do this for vectors. Legalize them and add patterns to emit the satuarting instructions. Differential revision: https://reviews.llvm.org/D71940
This commit is contained in:
Nemanja Ivanovic
parent
54ef354524
commit
be1be6dd59
@ -567,6 +567,12 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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}
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if (Subtarget.hasAltivec()) {
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for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
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setOperationAction(ISD::SADDSAT, VT, Legal);
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setOperationAction(ISD::SSUBSAT, VT, Legal);
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setOperationAction(ISD::UADDSAT, VT, Legal);
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setOperationAction(ISD::USUBSAT, VT, Legal);
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}
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// First set operation action for all vector types to expand. Then we
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// will selectively turn on ones that can be effectively codegen'd.
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for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
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@ -869,6 +869,20 @@ def : Pat<(v8i16 (rotl v8i16:$vA, v8i16:$vB)),
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def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)),
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(v4i32 (VRLW v4i32:$vA, v4i32:$vB))>;
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// Saturating adds/subtracts.
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def : Pat<(v16i8 (saddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDSBS $vA, $vB))>;
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def : Pat<(v16i8 (uaddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDUBS $vA, $vB))>;
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def : Pat<(v8i16 (saddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDSHS $vA, $vB))>;
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def : Pat<(v8i16 (uaddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDUHS $vA, $vB))>;
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def : Pat<(v4i32 (saddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDSWS $vA, $vB))>;
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def : Pat<(v4i32 (uaddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDUWS $vA, $vB))>;
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def : Pat<(v16i8 (ssubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBSBS $vA, $vB))>;
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def : Pat<(v16i8 (usubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBUBS $vA, $vB))>;
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def : Pat<(v8i16 (ssubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBSHS $vA, $vB))>;
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def : Pat<(v8i16 (usubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBUHS $vA, $vB))>;
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def : Pat<(v4i32 (ssubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBSWS $vA, $vB))>;
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def : Pat<(v4i32 (usubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBUWS $vA, $vB))>;
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// Loads.
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def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
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135
test/CodeGen/PowerPC/saturating-intrinsics.ll
Normal file
135
test/CodeGen/PowerPC/saturating-intrinsics.ll
Normal file
@ -0,0 +1,135 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
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; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
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define dso_local <16 x i8 > @vectorsaddb(<16 x i8 > %a, <16 x i8 > %b) {
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; CHECK-LABEL: vectorsaddb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddsbs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %call
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}
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define dso_local <16 x i8 > @vectorssubb(<16 x i8 > %a, <16 x i8 > %b) {
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; CHECK-LABEL: vectorssubb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsubsbs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %call
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}
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define dso_local <16 x i8 > @vectoruaddb(<16 x i8 > %a, <16 x i8 > %b) {
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; CHECK-LABEL: vectoruaddb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddubs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %call
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}
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define dso_local <16 x i8 > @vectorusubb(<16 x i8 > %a, <16 x i8 > %b) {
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; CHECK-LABEL: vectorusubb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsububs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %call
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}
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define dso_local <8 x i16 > @vectorsaddh(<8 x i16 > %a, <8 x i16 > %b) {
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; CHECK-LABEL: vectorsaddh:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddshs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %call
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}
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define dso_local <8 x i16 > @vectorssubh(<8 x i16 > %a, <8 x i16 > %b) {
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; CHECK-LABEL: vectorssubh:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsubshs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %call
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}
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define dso_local <8 x i16 > @vectoruaddh(<8 x i16 > %a, <8 x i16 > %b) {
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; CHECK-LABEL: vectoruaddh:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadduhs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %call
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}
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define dso_local <8 x i16 > @vectorusubh(<8 x i16 > %a, <8 x i16 > %b) {
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; CHECK-LABEL: vectorusubh:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsubuhs v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %call
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}
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define dso_local <4 x i32 > @vectorsaddw(<4 x i32 > %a, <4 x i32 > %b) {
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; CHECK-LABEL: vectorsaddw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vaddsws v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %call
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}
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define dso_local <4 x i32 > @vectorssubw(<4 x i32 > %a, <4 x i32 > %b) {
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; CHECK-LABEL: vectorssubw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsubsws v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %call
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}
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define dso_local <4 x i32 > @vectoruaddw(<4 x i32 > %a, <4 x i32 > %b) {
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; CHECK-LABEL: vectoruaddw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vadduws v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %call
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}
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define dso_local <4 x i32 > @vectorusubw(<4 x i32 > %a, <4 x i32 > %b) {
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; CHECK-LABEL: vectorusubw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsubuws v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%call = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %call
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}
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declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)
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declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)
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