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Allow BuildMI that helps automate construction of SSA information
llvm-svn: 4443
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d18210e53f
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@ -372,10 +372,11 @@ public:
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/// addRegOperand - Add a symbolic virtual register reference...
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///
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void addRegOperand(int reg) {
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void addRegOperand(int reg, bool isDef = false) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister));
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operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
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isDef));
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}
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/// addPCDispOperand - Add a PC relative displacement operand to the MI
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@ -29,8 +29,8 @@ struct MachineInstrBuilder {
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/// addReg - Add a new virtual register operand...
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///
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MachineInstrBuilder &addReg(int RegNo) {
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MI->addRegOperand(RegNo);
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MachineInstrBuilder &addReg(int RegNo, bool isDef = false) {
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MI->addRegOperand(RegNo, isDef);
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return *this;
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}
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@ -72,15 +72,31 @@ struct MachineInstrBuilder {
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};
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/// BuildMI - Builder interface. Specify how to create the initial instruction
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/// itself.
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/// itself. NumOperands is the number of operands to the machine instruction to
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/// allow for memory efficient representation of machine instructions.
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///
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inline MachineInstrBuilder BuildMI(MachineOpCode Opcode, unsigned NumOperands) {
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return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands, true, true));
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}
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/// BuildMI - This version of the builder inserts the built MachineInstr into
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/// the specified MachineBasicBlock.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, MachineOpCode Opcode,
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unsigned NumOperands) {
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return MachineInstrBuilder(new MachineInstr(BB, Opcode, NumOperands));
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}
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/// BuildMI - This version of the builder inserts the built MachineInstr into
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/// the specified MachineBasicBlock, and also sets up the first "operand" as a
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/// destination virtual register. NumOperands is the number of additional add*
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/// calls that are expected, it does not include the destination register.
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///
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inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, MachineOpCode Opcode,
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unsigned NumOperands, unsigned DestReg) {
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return MachineInstrBuilder(new MachineInstr(BB, Opcode,
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NumOperands+1)).addReg(DestReg,
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true);
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}
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#endif
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