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[PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang
This patch implements the vec_gen[b|h|w|d|q]m function prototypes in altivec.h in order to utilize the move to VSR with mask instructions introduced in Power10. Differential Revision: https://reviews.llvm.org/D82725
This commit is contained in:
Amy Kwan
parent
eaea7ba7a7
commit
be427da523
@ -481,6 +481,18 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_i64_ty], [llvm_v2i64_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<1>>]>;
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// P10 Move to VSR with Mask Intrinsics.
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def int_ppc_altivec_mtvsrbm : GCCBuiltin<"__builtin_altivec_mtvsrbm">,
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Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty], [IntrNoMem]>;
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def int_ppc_altivec_mtvsrhm : GCCBuiltin<"__builtin_altivec_mtvsrhm">,
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Intrinsic<[llvm_v8i16_ty], [llvm_i64_ty], [IntrNoMem]>;
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def int_ppc_altivec_mtvsrwm : GCCBuiltin<"__builtin_altivec_mtvsrwm">,
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Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty], [IntrNoMem]>;
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def int_ppc_altivec_mtvsrdm : GCCBuiltin<"__builtin_altivec_mtvsrdm">,
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Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty], [IntrNoMem]>;
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def int_ppc_altivec_mtvsrqm : GCCBuiltin<"__builtin_altivec_mtvsrqm">,
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Intrinsic<[llvm_v1i128_ty], [llvm_i64_ty], [IntrNoMem]>;
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// P10 Vector Parallel Bits Deposit/Extract Doubleword Builtins.
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def int_ppc_altivec_vpdepd : GCCBuiltin<"__builtin_altivec_vpdepd">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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@ -1054,22 +1054,28 @@ let Predicates = [IsISA3_1] in {
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v1i128:$vB))]>;
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def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB),
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"mtvsrbm $vD, $rB", IIC_VecGeneral,
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[]>;
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[(set v16i8:$vD,
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(int_ppc_altivec_mtvsrbm i64:$rB))]>;
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def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB),
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"mtvsrhm $vD, $rB", IIC_VecGeneral,
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[]>;
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[(set v8i16:$vD,
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(int_ppc_altivec_mtvsrhm i64:$rB))]>;
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def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB),
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"mtvsrwm $vD, $rB", IIC_VecGeneral,
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[]>;
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[(set v4i32:$vD,
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(int_ppc_altivec_mtvsrwm i64:$rB))]>;
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def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB),
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"mtvsrdm $vD, $rB", IIC_VecGeneral,
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[]>;
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[(set v2i64:$vD,
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(int_ppc_altivec_mtvsrdm i64:$rB))]>;
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def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB),
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"mtvsrqm $vD, $rB", IIC_VecGeneral,
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[]>;
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[(set v1i128:$vD,
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(int_ppc_altivec_mtvsrqm i64:$rB))]>;
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def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D),
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"mtvsrbmi $vD, $D", IIC_VecGeneral,
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[]>;
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[(set v16i8:$vD,
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(int_ppc_altivec_mtvsrbm imm:$D))]>;
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def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD),
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(ins vrrc:$vB, u1imm:$MP),
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"vcntmbb $rD, $vB, $MP", IIC_VecGeneral,
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@ -165,3 +165,109 @@ entry:
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%cnt = tail call i64 @llvm.ppc.altivec.vcntmbd(<2 x i64> %a, i32 0)
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ret i64 %cnt
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}
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declare <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64)
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declare <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64)
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declare <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64)
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declare <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64)
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declare <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64)
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define <16 x i8> @test_mtvsrbm(i64 %a) {
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; CHECK-LABEL: test_mtvsrbm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 %a)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi() {
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; CHECK-LABEL: test_mtvsrbmi:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 1
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 1)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi2() {
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; CHECK-LABEL: test_mtvsrbmi2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 255
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 255)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi3() {
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; CHECK-LABEL: test_mtvsrbmi3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 65535
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65535)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi4() {
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; CHECK-LABEL: test_mtvsrbmi4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 0
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65536)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi5() {
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; CHECK-LABEL: test_mtvsrbmi5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 10
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65546)
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ret <16 x i8> %mv
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}
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define <8 x i16> @test_mtvsrhm(i64 %a) {
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; CHECK-LABEL: test_mtvsrhm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrhm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64 %a)
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ret <8 x i16> %mv
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}
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define <4 x i32> @test_mtvsrwm(i64 %a) {
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; CHECK-LABEL: test_mtvsrwm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64 %a)
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ret <4 x i32> %mv
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}
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define <2 x i64> @test_mtvsrdm(i64 %a) {
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; CHECK-LABEL: test_mtvsrdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64 %a)
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ret <2 x i64> %mv
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}
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define <1 x i128> @test_mtvsrqm(i64 %a) {
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; CHECK-LABEL: test_mtvsrqm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrqm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64 %a)
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ret <1 x i128> %mv
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}
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