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[ARM] GlobalISel: Support G_ICMP for i32 and pointers

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Add support throughout the pipeline:
- mark as legal for s32 and pointers
- map to GPRs
- lower to a sequence of instructions, which moves 0 or 1 into the
  result register based on the flags set by a CMPrr

We have copied from FastISel a helper function which maps CmpInst
predicates into ARMCC codes. Ideally, we should be able to move it
somewhere that both FastISel and GlobalISel can use.

llvm-svn: 305672
This commit is contained in:
Diana Picus 2017-06-19 09:40:51 +00:00
parent 512ffd23a1
commit be5dc529e4
7 changed files with 576 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

105
lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -42,6 +42,10 @@ public:
private:
bool selectImpl(MachineInstr &I) const;
bool selectICmp(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) const;
const ARMBaseInstrInfo &TII;
const ARMBaseRegisterInfo &TRI;
const ARMBaseTargetMachine &TM;
@ -243,6 +247,105 @@ static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
return Opc;
}
static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
switch (Pred) {
// Needs two compares...
case CmpInst::FCMP_ONE:
case CmpInst::FCMP_UEQ:
default:
// AL is our "false" for now. The other two need more compares.
return ARMCC::AL;
case CmpInst::ICMP_EQ:
case CmpInst::FCMP_OEQ:
return ARMCC::EQ;
case CmpInst::ICMP_SGT:
case CmpInst::FCMP_OGT:
return ARMCC::GT;
case CmpInst::ICMP_SGE:
case CmpInst::FCMP_OGE:
return ARMCC::GE;
case CmpInst::ICMP_UGT:
case CmpInst::FCMP_UGT:
return ARMCC::HI;
case CmpInst::FCMP_OLT:
return ARMCC::MI;
case CmpInst::ICMP_ULE:
case CmpInst::FCMP_OLE:
return ARMCC::LS;
case CmpInst::FCMP_ORD:
return ARMCC::VC;
case CmpInst::FCMP_UNO:
return ARMCC::VS;
case CmpInst::FCMP_UGE:
return ARMCC::PL;
case CmpInst::ICMP_SLT:
case CmpInst::FCMP_ULT:
return ARMCC::LT;
case CmpInst::ICMP_SLE:
case CmpInst::FCMP_ULE:
return ARMCC::LE;
case CmpInst::FCMP_UNE:
case CmpInst::ICMP_NE:
return ARMCC::NE;
case CmpInst::ICMP_UGE:
return ARMCC::HS;
case CmpInst::ICMP_ULT:
return ARMCC::LO;
}
}
bool ARMInstructionSelector::selectICmp(MachineInstrBuilder &MIB,
const ARMBaseInstrInfo &TII,
MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) const {
auto &MBB = *MIB->getParent();
auto InsertBefore = std::next(MIB->getIterator());
auto &DebugLoc = MIB->getDebugLoc();
// Move 0 into the result register.
auto Mov0I = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::MOVi))
.addDef(MRI.createVirtualRegister(&ARM::GPRRegClass))
.addImm(0)
.add(predOps(ARMCC::AL))
.add(condCodeOp());
if (!constrainSelectedInstRegOperands(*Mov0I, TII, TRI, RBI))
return false;
// Perform the comparison.
auto LHSReg = MIB->getOperand(2).getReg();
auto RHSReg = MIB->getOperand(3).getReg();
assert(MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
MRI.getType(LHSReg).getSizeInBits() == 32 &&
MRI.getType(RHSReg).getSizeInBits() == 32 &&
"Unsupported types for comparison operation");
auto CmpI = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::CMPrr))
.addUse(LHSReg)
.addUse(RHSReg)
.add(predOps(ARMCC::AL));
if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
return false;
// Move 1 into the result register if the flags say so.
auto ResReg = MIB->getOperand(0).getReg();
auto Cond =
static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
auto ARMCond = getComparePred(Cond);
if (ARMCond == ARMCC::AL)
return false;
auto Mov1I = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::MOVCCi))
.addDef(ResReg)
.addUse(Mov0I->getOperand(0).getReg())
.addImm(1)
.add(predOps(ARMCond, ARM::CPSR));
if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
return false;
MIB->eraseFromParent();
return true;
}
bool ARMInstructionSelector::select(MachineInstr &I) const {
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");
@ -343,6 +446,8 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
I.setDesc(TII.get(COPY));
return selectCopy(I, TII, MRI, TRI, RBI);
}
case G_ICMP:
return selectICmp(MIB, TII, MRI, TRI, RBI);
case G_GEP:
I.setDesc(TII.get(ARM::ADDrr));
MIB.add(predOps(ARMCC::AL)).add(condCodeOp());

4
lib/Target/ARM/ARMLegalizerInfo.cpp
View File

@ -86,6 +86,10 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({G_CONSTANT, s32}, Legal);
setAction({G_ICMP, s1}, Legal);
for (auto Ty : {s32, p0})
setAction({G_ICMP, 1, Ty}, Legal);
if (!ST.useSoftFloat() && ST.hasVFP2()) {
setAction({G_FADD, s32}, Legal);
setAction({G_FADD, s64}, Legal);

10
lib/Target/ARM/ARMRegisterBankInfo.cpp
View File

@ -255,6 +255,16 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
break;
case G_ICMP: {
LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
(void)Ty2;
assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP");
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
&ARM::ValueMappings[ARM::GPR3OpsIdx],
&ARM::ValueMappings[ARM::GPR3OpsIdx]});
break;
}
case G_MERGE_VALUES: {
// We only support G_MERGE_VALUES for creating a double precision floating
// point value out of two GPRs.

373
test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir Normal file
View File

@ -0,0 +1,373 @@
# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_icmp_eq_s32() { ret void }
define void @test_icmp_ne_s32() { ret void }
define void @test_icmp_ugt_s32() { ret void }
define void @test_icmp_uge_s32() { ret void }
define void @test_icmp_ult_s32() { ret void }
define void @test_icmp_ule_s32() { ret void }
define void @test_icmp_sgt_s32() { ret void }
define void @test_icmp_sge_s32() { ret void }
define void @test_icmp_slt_s32() { ret void }
define void @test_icmp_sle_s32() { ret void }
...
---
name: test_icmp_eq_s32
# CHECK-LABEL: name: test_icmp_eq_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ne_s32
# CHECK-LABEL: name: test_icmp_ne_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(ne), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ugt_s32
# CHECK-LABEL: name: test_icmp_ugt_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_uge_s32
# CHECK-LABEL: name: test_icmp_uge_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(uge), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 2, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ult_s32
# CHECK-LABEL: name: test_icmp_ult_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 3, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ule_s32
# CHECK-LABEL: name: test_icmp_ule_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(ule), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_sgt_s32
# CHECK-LABEL: name: test_icmp_sgt_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_sge_s32
# CHECK-LABEL: name: test_icmp_sge_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(sge), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_slt_s32
# CHECK-LABEL: name: test_icmp_slt_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(slt), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_sle_s32
# CHECK-LABEL: name: test_icmp_sle_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = G_ICMP intpred(sle), %0(s32), %1
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RET]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...

26
test/CodeGen/ARM/GlobalISel/arm-isel.ll
View File

@ -359,3 +359,29 @@ entry:
%v = fadd double %f0, %f1
ret double %v
}
define arm_aapcscc i32 @test_cmp_i32_eq(i32 %a, i32 %b) {
; CHECK-LABEL: test_cmp_i32_eq:
; CHECK: mov [[V:r[0-9]+]], #0
; CHECK: cmp r0, r1
; CHECK: moveq [[V]], #1
; CHECK: and r0, [[V]], #1
; CHECK: bx lr
entry:
%v = icmp eq i32 %a, %b
%r = zext i1 %v to i32
ret i32 %r
}
define arm_aapcscc i32 @test_cmp_ptr_neq(double *%a, double *%b) {
; CHECK-LABEL: test_cmp_ptr_neq:
; CHECK: mov [[V:r[0-9]+]], #0
; CHECK: cmp r0, r1
; CHECK: movne [[V]], #1
; CHECK: and r0, [[V]], #1
; CHECK: bx lr
entry:
%v = icmp ne double * %a, %b
%r = zext i1 %v to i32
ret i32 %r
}

28
test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
View File

@ -35,6 +35,8 @@
define void @test_constants() { ret void }
define void @test_icmp_eq_s32() { ret void }
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
@ -691,6 +693,32 @@ body: |
BX_RET 14, _, implicit %r0
...
---
name: test_icmp_eq_s32
# CHECK-LABEL: name: test_icmp_eq_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
; G_ICMP with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
%3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: false

30
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
View File

@ -34,6 +34,8 @@
define void @test_trunc_s32_16() { ret void }
define void @test_icmp_eq_s32() { ret void }
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
@ -711,6 +713,34 @@ body: |
BX_RET 14, _, implicit %r0
...
---
name: test_icmp_eq_s32
# CHECK-LABEL: name: test_icmp_eq_s32
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: true