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Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0 (and move a function)
This happens all the time on PPC for bool values, e.g. eliminating a xori in inverted-bool-compares.ll. This should be added to the dag combiner as well. llvm-svn: 23403
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@ -580,6 +580,80 @@ SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) {
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return SDOperand(Reg, 0);
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return SDOperand(Reg, 0);
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}
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}
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/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
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/// this predicate to simplify operations downstream. V and Mask are known to
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/// be the same type.
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static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
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const TargetLowering &TLI) {
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unsigned SrcBits;
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if (Mask == 0) return true;
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// If we know the result of a setcc has the top bits zero, use this info.
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switch (Op.getOpcode()) {
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::AND:
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
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// FALL THROUGH
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask << ShAmt->getValue();
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SrcBits = MVT::getSizeInBits(Op.getValueType());
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if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::SHL:
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// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask >> ShAmt->getValue();
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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// TODO we could handle some SRA cases here.
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default: break;
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}
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return false;
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}
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SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
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SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
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SDOperand N2, ISD::CondCode Cond) {
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SDOperand N2, ISD::CondCode Cond) {
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// These setcc operations always fold.
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// These setcc operations always fold.
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@ -816,6 +890,18 @@ SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
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// FIXME: move this stuff to the DAG Combiner when it exists!
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// FIXME: move this stuff to the DAG Combiner when it exists!
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// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
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if (N1.getOpcode() == ISD::XOR)
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if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N2)) {
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// If we know that all of the inverted bits are zero, don't bother
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// performing the inversion.
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if (MaskedValueIsZero(N1.getOperand(0), ~XORC->getValue(), TLI))
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return getSetCC(VT, N1.getOperand(0),
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getConstant(XORC->getValue()^RHSC->getValue(),
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N1.getValueType()), Cond);
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}
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// Simplify (X+Z) == X --> Z == 0
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// Simplify (X+Z) == X --> Z == 0
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if (N1.getOperand(0) == N2)
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if (N1.getOperand(0) == N2)
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return getSetCC(VT, N1.getOperand(1),
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return getSetCC(VT, N1.getOperand(1),
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@ -1126,78 +1212,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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return SDOperand(N, 0);
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return SDOperand(N, 0);
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}
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}
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/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
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/// this predicate to simplify operations downstream. V and Mask are known to
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/// be the same type.
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static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
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const TargetLowering &TLI) {
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unsigned SrcBits;
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if (Mask == 0) return true;
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// If we know the result of a setcc has the top bits zero, use this info.
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switch (Op.getOpcode()) {
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::AND:
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
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// FALL THROUGH
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask << ShAmt->getValue();
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SrcBits = MVT::getSizeInBits(Op.getValueType());
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if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::SHL:
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// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask >> ShAmt->getValue();
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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// TODO we could handle some SRA cases here.
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default: break;
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}
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return false;
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}
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SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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