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Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure

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lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.

llvm-svn: 148044
This commit is contained in:
Elena Demikhovsky 2012-01-12 20:33:10 +00:00
parent 4967772ebc
commit beb66de0f9
2 changed files with 14 additions and 2 deletions
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6
lib/Target/X86/X86ISelLowering.cpp
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@ -6464,6 +6464,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
unsigned NumElems = VT.getVectorNumElements();
bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
bool V1IsSplat = false;
bool V2IsSplat = false;
@ -6475,7 +6476,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef");
if (V1IsUndef && V2IsUndef)
return DAG.getUNDEF(VT);
assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
// Vector shuffle lowering takes 3 steps:
//

10
test/CodeGen/X86/avx-shuffle.ll
View File

@ -54,4 +54,12 @@ entry:
; CHECK-NOT: vinsertf128
%shuffle.i = shufflevector <2 x double> %1, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
ret <4 x double> %shuffle.i
}
}
define <16 x i16> @test7(<4 x i16> %a) nounwind {
; CHECK: test7
%b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <16 x i16> %b
}