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misched: disable SSA check pending PR13112.
llvm-svn: 158461
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@ -413,8 +413,10 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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// SSA defs do not have output/anti dependencies.
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// The current operand is a def, so we have at least one.
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if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
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return;
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//
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// FIXME: This optimization is disabled pending PR13112.
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//if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
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// return;
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// Add output dependence to the next nearest def of this vreg.
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//
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