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[RISCV] Implement isLegalAddressingMode for RISC-V
This has no impact on codegen for the current RISC-V unit tests or my small benchmark set and very minor changes in a few programs in the GCC torture suite. Based on this, I haven't been able to produce a representative test program that demonstrates a benefit from isLegalAddressingMode. I'm committing the patch anyway, on the basis that presenting accurate information to the target-independent code is preferable to relying on incorrect generic assumptions. llvm-svn: 330932
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@ -157,6 +157,32 @@ EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
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return VT.changeVectorElementTypeToInteger();
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}
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bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
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const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I) const {
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// No global is ever allowed as a base.
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if (AM.BaseGV)
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return false;
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// Require a 12-bit signed offset.
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if (!isInt<12>(AM.BaseOffs))
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return false;
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switch (AM.Scale) {
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case 0: // "r+i" or just "i", depending on HasBaseReg.
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break;
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case 1:
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if (!AM.HasBaseReg) // allow "r+i".
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break;
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return false; // disallow "r+r" or "r+r+i".
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default:
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return false;
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}
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return true;
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}
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// Changes the condition code and swaps operands if necessary, so the SetCC
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// operation matches one of the comparisons supported directly in the RISC-V
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// ISA.
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@ -39,6 +39,10 @@ public:
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explicit RISCVTargetLowering(const TargetMachine &TM,
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const RISCVSubtarget &STI);
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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