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[AVX-512] Remove AddedComplexity from masked operations. The size of the patterns already increases their priority.
llvm-svn: 295619
This commit is contained in:
Craig Topper
parent
660cf776ec
commit
befbc1c4c5
@ -210,7 +210,7 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F,
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Pattern, itin>;
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// Prefer over VMOV*rrk Pat<>
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let AddedComplexity = 20, isCommutable = IsKCommutable in
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let isCommutable = IsKCommutable in
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def NAME#k: AVX512<O, F, Outs, MaskingIns,
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OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
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"$dst {${mask}}, "#IntelSrcAsm#"}",
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@ -222,7 +222,7 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F,
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// Zero mask does not add any restrictions to commute operands transformation.
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// So, it is Ok to use IsCommutable instead of IsKCommutable.
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let AddedComplexity = 30, isCommutable = IsCommutable in // Prefer over VMOV*rrkz Pat<>
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let isCommutable = IsCommutable in // Prefer over VMOV*rrkz Pat<>
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def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
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OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
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"$dst {${mask}} {z}, "#IntelSrcAsm#"}",
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@ -883,7 +883,6 @@ multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
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(SrcInfo.VT (scalar_to_vector
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(SrcInfo.ScalarLdFrag addr:$src))))),
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(!cast<Instruction>(NAME#DestInfo.ZSuffix#m) addr:$src)>;
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let AddedComplexity = 20 in
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def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
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(X86VBroadcast
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(SrcInfo.VT (scalar_to_vector
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@ -891,7 +890,6 @@ multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
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DestInfo.RC:$src0)),
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(!cast<Instruction>(NAME#DestInfo.ZSuffix#mk)
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DestInfo.RC:$src0, DestInfo.KRCWM:$mask, addr:$src)>;
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let AddedComplexity = 30 in
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def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
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(X86VBroadcast
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(SrcInfo.VT (scalar_to_vector
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@ -2001,22 +1999,20 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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let AddedComplexity = 20 in {
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def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,
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(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2)))], NoItinerary>;
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def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,
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(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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}
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(i32 imm:$src2)))], NoItinerary>;
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def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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}
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}
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@ -4920,7 +4916,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _,
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def : Pat<(_.VT (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2)))),
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(!cast<Instruction>(InstrStr#_.ZSuffix##rm)
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_.RC:$src1, addr:$src2)>;
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let AddedComplexity = 20 in {
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(X86vsrav _.RC:$src1, _.RC:$src2), _.RC:$src0)),
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(!cast<Instruction>(InstrStr#_.ZSuffix#rrk) _.RC:$src0,
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@ -4930,8 +4925,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _,
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_.RC:$src0)),
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(!cast<Instruction>(InstrStr#_.ZSuffix##rmk) _.RC:$src0,
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_.KRC:$mask, _.RC:$src1, addr:$src2)>;
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}
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let AddedComplexity = 30 in {
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(X86vsrav _.RC:$src1, _.RC:$src2), _.ImmAllZerosV)),
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(!cast<Instruction>(InstrStr#_.ZSuffix#rrkz) _.KRC:$mask,
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@ -4941,7 +4934,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _,
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_.ImmAllZerosV)),
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(!cast<Instruction>(InstrStr#_.ZSuffix##rmkz) _.KRC:$mask,
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_.RC:$src1, addr:$src2)>;
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}
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}
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}
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@ -4953,14 +4945,12 @@ multiclass avx512_var_shift_int_lowering_mb<string InstrStr, X86VectorVTInfo _,
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(X86VBroadcast (_.ScalarLdFrag addr:$src2)))),
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(!cast<Instruction>(InstrStr#_.ZSuffix##rmb)
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_.RC:$src1, addr:$src2)>;
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let AddedComplexity = 20 in
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(X86vsrav _.RC:$src1,
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(X86VBroadcast (_.ScalarLdFrag addr:$src2))),
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_.RC:$src0)),
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(!cast<Instruction>(InstrStr#_.ZSuffix##rmbk) _.RC:$src0,
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_.KRC:$mask, _.RC:$src1, addr:$src2)>;
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let AddedComplexity = 30 in
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(X86vsrav _.RC:$src1,
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(X86VBroadcast (_.ScalarLdFrag addr:$src2))),
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@ -6824,7 +6814,7 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
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/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
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multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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let AddedComplexity = 20 , Predicates = [HasAVX512] in {
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let Predicates = [HasAVX512] in {
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defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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@ -8957,7 +8947,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}// Constraints = "$src1 = $dst"
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// Additional patterns for matching passthru operand in other positions.
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let AddedComplexity = 20 in {
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
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_.RC:$src1)),
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@ -8968,7 +8957,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
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_.RC:$src1)),
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(!cast<Instruction>(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
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_.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
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}
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// Additional patterns for matching loads in other positions.
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def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)),
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@ -8983,7 +8971,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// Additional patterns for matching zero masking with loads in other
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// positions.
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let AddedComplexity = 30 in {
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(OpNode (bitconvert (_.LdFrag addr:$src3)),
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_.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
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@ -8996,18 +8983,15 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
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_.ImmAllZerosV)),
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(!cast<Instruction>(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
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_.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
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}
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// Additional patterns for matching masked loads with different
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// operand orders.
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let AddedComplexity = 20 in {
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def : Pat<(_.VT (vselect _.KRCWM:$mask,
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(OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
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_.RC:$src2, (i8 imm:$src4)),
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_.RC:$src1)),
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(!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
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_.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
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}
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}
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multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
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