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[AVX-512] Remove AddedComplexity from masked operations. The size of the patterns already increases their priority.

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llvm-svn: 295619
This commit is contained in:
Craig Topper 2017-02-19 21:44:35 +00:00
parent 660cf776ec
commit befbc1c4c5
1 changed files with 16 additions and 32 deletions
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48
lib/Target/X86/X86InstrAVX512.td
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@ -210,7 +210,7 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F,
Pattern, itin>; Pattern, itin>;
// Prefer over VMOV*rrk Pat<> // Prefer over VMOV*rrk Pat<>
let AddedComplexity = 20, isCommutable = IsKCommutable in let isCommutable = IsKCommutable in
def NAME#k: AVX512<O, F, Outs, MaskingIns, def NAME#k: AVX512<O, F, Outs, MaskingIns,
OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"# OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
"$dst {${mask}}, "#IntelSrcAsm#"}", "$dst {${mask}}, "#IntelSrcAsm#"}",
@ -222,7 +222,7 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F,
// Zero mask does not add any restrictions to commute operands transformation. // Zero mask does not add any restrictions to commute operands transformation.
// So, it is Ok to use IsCommutable instead of IsKCommutable. // So, it is Ok to use IsCommutable instead of IsKCommutable.
let AddedComplexity = 30, isCommutable = IsCommutable in // Prefer over VMOV*rrkz Pat<> let isCommutable = IsCommutable in // Prefer over VMOV*rrkz Pat<>
def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns, def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"# OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
"$dst {${mask}} {z}, "#IntelSrcAsm#"}", "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
@ -883,7 +883,6 @@ multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
(SrcInfo.VT (scalar_to_vector (SrcInfo.VT (scalar_to_vector
(SrcInfo.ScalarLdFrag addr:$src))))), (SrcInfo.ScalarLdFrag addr:$src))))),
(!cast<Instruction>(NAME#DestInfo.ZSuffix#m) addr:$src)>; (!cast<Instruction>(NAME#DestInfo.ZSuffix#m) addr:$src)>;
let AddedComplexity = 20 in
def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
(X86VBroadcast (X86VBroadcast
(SrcInfo.VT (scalar_to_vector (SrcInfo.VT (scalar_to_vector
@ -891,7 +890,6 @@ multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
DestInfo.RC:$src0)), DestInfo.RC:$src0)),
(!cast<Instruction>(NAME#DestInfo.ZSuffix#mk) (!cast<Instruction>(NAME#DestInfo.ZSuffix#mk)
DestInfo.RC:$src0, DestInfo.KRCWM:$mask, addr:$src)>; DestInfo.RC:$src0, DestInfo.KRCWM:$mask, addr:$src)>;
let AddedComplexity = 30 in
def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask, def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
(X86VBroadcast (X86VBroadcast
(SrcInfo.VT (scalar_to_vector (SrcInfo.VT (scalar_to_vector
@ -2001,22 +1999,20 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
[(set _.KRC:$dst,(or _.KRCWM:$mask, [(set _.KRC:$dst,(or _.KRCWM:$mask,
(OpNode (_.VT _.RC:$src1), (OpNode (_.VT _.RC:$src1),
(i32 imm:$src2))))], NoItinerary>, EVEX_K; (i32 imm:$src2))))], NoItinerary>, EVEX_K;
let AddedComplexity = 20 in { def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst), (ins _.MemOp:$src1, i32u8imm:$src2),
(ins _.MemOp:$src1, i32u8imm:$src2), OpcodeStr##_.Suffix##
OpcodeStr##_.Suffix## "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.KRC:$dst,
[(set _.KRC:$dst,
(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
(i32 imm:$src2)))], NoItinerary>;
def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
OpcodeStr##_.Suffix##
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
[(set _.KRC:$dst,(or _.KRCWM:$mask,
(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))), (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
(i32 imm:$src2))))], NoItinerary>, EVEX_K; (i32 imm:$src2)))], NoItinerary>;
} def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
OpcodeStr##_.Suffix##
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
[(set _.KRC:$dst,(or _.KRCWM:$mask,
(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
(i32 imm:$src2))))], NoItinerary>, EVEX_K;
} }
} }
@ -4920,7 +4916,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _,
def : Pat<(_.VT (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2)))), def : Pat<(_.VT (X86vsrav _.RC:$src1, (bitconvert (_.LdFrag addr:$src2)))),
(!cast<Instruction>(InstrStr#_.ZSuffix##rm) (!cast<Instruction>(InstrStr#_.ZSuffix##rm)
_.RC:$src1, addr:$src2)>; _.RC:$src1, addr:$src2)>;
let AddedComplexity = 20 in {
def : Pat<(_.VT (vselect _.KRCWM:$mask, def : Pat<(_.VT (vselect _.KRCWM:$mask,
(X86vsrav _.RC:$src1, _.RC:$src2), _.RC:$src0)), (X86vsrav _.RC:$src1, _.RC:$src2), _.RC:$src0)),
(!cast<Instruction>(InstrStr#_.ZSuffix#rrk) _.RC:$src0, (!cast<Instruction>(InstrStr#_.ZSuffix#rrk) _.RC:$src0,
@ -4930,8 +4925,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _,
_.RC:$src0)), _.RC:$src0)),
(!cast<Instruction>(InstrStr#_.ZSuffix##rmk) _.RC:$src0, (!cast<Instruction>(InstrStr#_.ZSuffix##rmk) _.RC:$src0,
_.KRC:$mask, _.RC:$src1, addr:$src2)>; _.KRC:$mask, _.RC:$src1, addr:$src2)>;
}
let AddedComplexity = 30 in {
def : Pat<(_.VT (vselect _.KRCWM:$mask, def : Pat<(_.VT (vselect _.KRCWM:$mask,
(X86vsrav _.RC:$src1, _.RC:$src2), _.ImmAllZerosV)), (X86vsrav _.RC:$src1, _.RC:$src2), _.ImmAllZerosV)),
(!cast<Instruction>(InstrStr#_.ZSuffix#rrkz) _.KRC:$mask, (!cast<Instruction>(InstrStr#_.ZSuffix#rrkz) _.KRC:$mask,
@ -4941,7 +4934,6 @@ multiclass avx512_var_shift_int_lowering<string InstrStr, X86VectorVTInfo _,
_.ImmAllZerosV)), _.ImmAllZerosV)),
(!cast<Instruction>(InstrStr#_.ZSuffix##rmkz) _.KRC:$mask, (!cast<Instruction>(InstrStr#_.ZSuffix##rmkz) _.KRC:$mask,
_.RC:$src1, addr:$src2)>; _.RC:$src1, addr:$src2)>;
}
} }
} }
@ -4953,14 +4945,12 @@ multiclass avx512_var_shift_int_lowering_mb<string InstrStr, X86VectorVTInfo _,
(X86VBroadcast (_.ScalarLdFrag addr:$src2)))), (X86VBroadcast (_.ScalarLdFrag addr:$src2)))),
(!cast<Instruction>(InstrStr#_.ZSuffix##rmb) (!cast<Instruction>(InstrStr#_.ZSuffix##rmb)
_.RC:$src1, addr:$src2)>; _.RC:$src1, addr:$src2)>;
let AddedComplexity = 20 in
def : Pat<(_.VT (vselect _.KRCWM:$mask, def : Pat<(_.VT (vselect _.KRCWM:$mask,
(X86vsrav _.RC:$src1, (X86vsrav _.RC:$src1,
(X86VBroadcast (_.ScalarLdFrag addr:$src2))), (X86VBroadcast (_.ScalarLdFrag addr:$src2))),
_.RC:$src0)), _.RC:$src0)),
(!cast<Instruction>(InstrStr#_.ZSuffix##rmbk) _.RC:$src0, (!cast<Instruction>(InstrStr#_.ZSuffix##rmbk) _.RC:$src0,
_.KRC:$mask, _.RC:$src1, addr:$src2)>; _.KRC:$mask, _.RC:$src1, addr:$src2)>;
let AddedComplexity = 30 in
def : Pat<(_.VT (vselect _.KRCWM:$mask, def : Pat<(_.VT (vselect _.KRCWM:$mask,
(X86vsrav _.RC:$src1, (X86vsrav _.RC:$src1,
(X86VBroadcast (_.ScalarLdFrag addr:$src2))), (X86VBroadcast (_.ScalarLdFrag addr:$src2))),
@ -6824,7 +6814,7 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode, multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
X86VectorVTInfo _> { X86VectorVTInfo _> {
let AddedComplexity = 20 , Predicates = [HasAVX512] in { let Predicates = [HasAVX512] in {
defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2), OpcodeStr, (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2", "$src2, $src1", "$src1, $src2",
@ -8957,7 +8947,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
}// Constraints = "$src1 = $dst" }// Constraints = "$src1 = $dst"
// Additional patterns for matching passthru operand in other positions. // Additional patterns for matching passthru operand in other positions.
let AddedComplexity = 20 in {
def : Pat<(_.VT (vselect _.KRCWM:$mask, def : Pat<(_.VT (vselect _.KRCWM:$mask,
(OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)), (OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
_.RC:$src1)), _.RC:$src1)),
@ -8968,7 +8957,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
_.RC:$src1)), _.RC:$src1)),
(!cast<Instruction>(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask, (!cast<Instruction>(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
_.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>; _.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
}
// Additional patterns for matching loads in other positions. // Additional patterns for matching loads in other positions.
def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)), def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)),
@ -8983,7 +8971,6 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
// Additional patterns for matching zero masking with loads in other // Additional patterns for matching zero masking with loads in other
// positions. // positions.
let AddedComplexity = 30 in {
def : Pat<(_.VT (vselect _.KRCWM:$mask, def : Pat<(_.VT (vselect _.KRCWM:$mask,
(OpNode (bitconvert (_.LdFrag addr:$src3)), (OpNode (bitconvert (_.LdFrag addr:$src3)),
_.RC:$src2, _.RC:$src1, (i8 imm:$src4)), _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
@ -8996,18 +8983,15 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
_.ImmAllZerosV)), _.ImmAllZerosV)),
(!cast<Instruction>(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask, (!cast<Instruction>(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
_.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
}
// Additional patterns for matching masked loads with different // Additional patterns for matching masked loads with different
// operand orders. // operand orders.
let AddedComplexity = 20 in {
def : Pat<(_.VT (vselect _.KRCWM:$mask, def : Pat<(_.VT (vselect _.KRCWM:$mask,
(OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)), (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
_.RC:$src2, (i8 imm:$src4)), _.RC:$src2, (i8 imm:$src4)),
_.RC:$src1)), _.RC:$src1)),
(!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask, (!cast<Instruction>(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
_.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>; _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
}
} }
multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{ multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{