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[ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes
ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for the Thumb1 target. This causes generation of redundant code and affects performance. This fixes PR34106: https://bugs.llvm.org/show_bug.cgi?id=34106 Differential Revision: https://reviews.llvm.org/D36467 llvm-svn: 311649
This commit is contained in:
Evgeny Astigeevich
parent
9e3f7a9eb4
commit
bf02c23ee9
@ -12383,6 +12383,21 @@ bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
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}
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}
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bool ARMTargetLowering::isLegalT1ScaledAddressingMode(const AddrMode &AM,
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EVT VT) const {
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const int Scale = AM.Scale;
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// Negative scales are not supported in Thumb1.
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if (Scale < 0)
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return false;
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// Thumb1 addressing modes do not support register scaling excepting the
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// following cases:
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// 1. Scale == 1 means no scaling.
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// 2. Scale == 2 this can be lowered to r + r if there is no base register.
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return (Scale == 1) || (!AM.HasBaseReg && Scale == 2);
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}
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
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@ -12399,10 +12414,6 @@ bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
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switch (AM.Scale) {
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case 0: // no scale reg, must be "r+i" or "r", or "i".
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break;
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case 1:
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if (Subtarget->isThumb1Only())
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return false;
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LLVM_FALLTHROUGH;
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default:
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// ARM doesn't support any R+R*scale+imm addr modes.
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if (AM.BaseOffs)
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@ -12411,6 +12422,9 @@ bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
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if (!VT.isSimple())
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return false;
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if (Subtarget->isThumb1Only())
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return isLegalT1ScaledAddressingMode(AM, VT);
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if (Subtarget->isThumb2())
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return isLegalT2ScaledAddressingMode(AM, VT);
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@ -329,6 +329,10 @@ class InstrItineraryData;
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bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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/// \brief Returns true if the addresing mode representing by AM is legal
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/// for the Thumb1 target, for a load/store of the specified type.
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bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can
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/// compare a register against the immediate without having to materialize
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45
test/CodeGen/Thumb/addr-modes.ll
Normal file
45
test/CodeGen/Thumb/addr-modes.ll
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@ -0,0 +1,45 @@
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; REQUIRES: asserts
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; RUN: llc < %s -debug-only=codegenprepare -o /dev/null 2>&1 | FileCheck %s
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; These are regression tests for
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; https://bugs.llvm.org/show_bug.cgi?id=34106
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; "ARMTargetLowering::isLegalAddressingMode can accept incorrect
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; addressing modes for Thumb1 target"
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;
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; The Thumb1 target addressing modes don't support scaling.
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; It supports: r1 + r2, where r1 and r2 can be the same register.
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-arm-none-eabi"
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; Test case 01: %n is scaled by 4 (size of i32).
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; Expected: GEP cannot be folded into LOAD.
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; CHECK: local addrmode: [Base:%arrayidx]
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define i32 @load01(i32* %p, i32 %n) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %p, i32 %n
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%0 = load i32, i32* %arrayidx, align 4
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ret i32 %0
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}
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; Test case 02: No scale of %n is needed because the size of i8 is 1.
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; Expected: GEP can be folded into LOAD.
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; CHECK: local addrmode: [Base:%p + 1*%n]
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define i8 @load02(i8* %p, i32 %n) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i8, i8* %p, i32 %n
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%0 = load i8, i8* %arrayidx
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ret i8 %0
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}
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; Test case 03: 2*%x can be represented as %x + %x.
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; Expected: GEP can be folded into LOAD.
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; CHECK: local addrmode: [2*%x]
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define i32 @load03(i32 %x) nounwind {
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entry:
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%mul = shl nsw i32 %x, 1
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%0 = inttoptr i32 %mul to i32*
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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122
test/Transforms/LoopStrengthReduce/illegal-addr-modes.ll
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122
test/Transforms/LoopStrengthReduce/illegal-addr-modes.ll
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@ -0,0 +1,122 @@
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; RUN: opt < %s -loop-reduce -S | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-arm-none-eabi"
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; These are regression tests for
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; https://bugs.llvm.org/show_bug.cgi?id=34106
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; "ARMTargetLowering::isLegalAddressingMode can accept incorrect
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; addressing modes for Thumb1 target"
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; https://reviews.llvm.org/D34583
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; "[LSR] Narrow search space by filtering non-optimal formulae with the
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; same ScaledReg and Scale."
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;
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; Due to a bug in ARMTargetLowering::isLegalAddressingMode LSR got
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; 4*reg({0,+,-1}) and -4*reg({0,+,-1}) had the same cost for the Thumb1 target.
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; Another issue was that LSR got that -1*reg was free for the Thumb1 target.
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; Test case 01: -1*reg is not free for the Thumb1 target.
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;
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; CHECK-LABEL: @negativeOneCase
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; CHECK-NOT: mul
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; CHECK: ret i8
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define i8* @negativeOneCase(i8* returned %a, i8* nocapture readonly %b, i32 %n) nounwind {
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entry:
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%add.ptr = getelementptr inbounds i8, i8* %a, i32 -1
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br label %while.cond
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while.cond: ; preds = %while.cond, %entry
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%p.0 = phi i8* [ %add.ptr, %entry ], [ %incdec.ptr, %while.cond ]
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%incdec.ptr = getelementptr inbounds i8, i8* %p.0, i32 1
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%0 = load i8, i8* %incdec.ptr, align 1
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%cmp = icmp eq i8 %0, 0
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br i1 %cmp, label %while.cond2.preheader, label %while.cond
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while.cond2.preheader: ; preds = %while.cond
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br label %while.cond2
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while.cond2: ; preds = %while.cond2.preheader, %while.body5
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%b.addr.0 = phi i8* [ %incdec.ptr6, %while.body5 ], [ %b, %while.cond2.preheader ]
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%n.addr.0 = phi i32 [ %dec, %while.body5 ], [ %n, %while.cond2.preheader ]
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%p.1 = phi i8* [ %incdec.ptr7, %while.body5 ], [ %incdec.ptr, %while.cond2.preheader ]
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%cmp3 = icmp eq i32 %n.addr.0, 0
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br i1 %cmp3, label %while.end8, label %while.body5
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while.body5: ; preds = %while.cond2
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%dec = add i32 %n.addr.0, -1
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%incdec.ptr6 = getelementptr inbounds i8, i8* %b.addr.0, i32 1
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%1 = load i8, i8* %b.addr.0, align 1
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%incdec.ptr7 = getelementptr inbounds i8, i8* %p.1, i32 1
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store i8 %1, i8* %p.1, align 1
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br label %while.cond2
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while.end8: ; preds = %while.cond2
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%scevgep = getelementptr i8, i8* %incdec.ptr, i32 %n
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store i8 0, i8* %scevgep, align 1
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ret i8* %a
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}
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; Test case 02: 4*reg({0,+,-1}) and -4*reg({0,+,-1}) are not supported for
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; the Thumb1 target.
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;
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; CHECK-LABEL: @negativeFourCase
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; CHECK-NOT: mul
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; CHECK: ret void
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define void @negativeFourCase(i8* %ptr1, i32* %ptr2) nounwind {
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entry:
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br label %for.cond6.preheader.us.i.i
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for.cond6.preheader.us.i.i: ; preds = %if.end48.us.i.i, %entry
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%addr.0108.us.i.i = phi i8* [ %scevgep.i.i, %if.end48.us.i.i ], [ %ptr1, %entry ]
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%inc49.us.i.i = phi i32 [ %inc50.us.i.i, %if.end48.us.i.i ], [ 0, %entry ]
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%c1.0104.us.i.i = phi i32* [ %c0.0103.us.i.i, %if.end48.us.i.i ], [ %ptr2, %entry ]
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%c0.0103.us.i.i = phi i32* [ %c1.0104.us.i.i, %if.end48.us.i.i ], [ %ptr2, %entry ]
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br label %for.body8.us.i.i
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if.end48.us.i.i: ; preds = %for.inc.us.i.i
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%scevgep.i.i = getelementptr i8, i8* %addr.0108.us.i.i, i32 256
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%inc50.us.i.i = add nuw nsw i32 %inc49.us.i.i, 1
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%exitcond110.i.i = icmp eq i32 %inc50.us.i.i, 256
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br i1 %exitcond110.i.i, label %exit.i, label %for.cond6.preheader.us.i.i
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for.body8.us.i.i: ; preds = %for.inc.us.i.i, %for.cond6.preheader.us.i.i
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%addr.198.us.i.i = phi i8* [ %addr.0108.us.i.i, %for.cond6.preheader.us.i.i ], [ %incdec.ptr.us.i.i, %for.inc.us.i.i ]
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%inc.196.us.i.i = phi i32 [ 0, %for.cond6.preheader.us.i.i ], [ %inc.2.us.i.i, %for.inc.us.i.i ]
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%c.093.us.i.i = phi i32 [ 0, %for.cond6.preheader.us.i.i ], [ %inc43.us.i.i, %for.inc.us.i.i ]
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%incdec.ptr.us.i.i = getelementptr inbounds i8, i8* %addr.198.us.i.i, i32 1
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%0 = load i8, i8* %addr.198.us.i.i, align 1
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%cmp9.us.i.i = icmp eq i8 %0, -1
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br i1 %cmp9.us.i.i, label %if.end37.us.i.i, label %if.else.us.i.i
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if.else.us.i.i: ; preds = %for.body8.us.i.i
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%add12.us.i.i = add nuw nsw i32 %c.093.us.i.i, 1
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%arrayidx13.us.i.i = getelementptr inbounds i32, i32* %c1.0104.us.i.i, i32 %add12.us.i.i
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%1 = load i32, i32* %arrayidx13.us.i.i, align 4
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%arrayidx16.us.i.i = getelementptr inbounds i32, i32* %c1.0104.us.i.i, i32 %c.093.us.i.i
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%2 = load i32, i32* %arrayidx16.us.i.i, align 4
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%sub19.us.i.i = add nsw i32 %c.093.us.i.i, -1
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%arrayidx20.us.i.i = getelementptr inbounds i32, i32* %c1.0104.us.i.i, i32 %sub19.us.i.i
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%3 = load i32, i32* %arrayidx20.us.i.i, align 4
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br label %if.end37.us.i.i
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if.end37.us.i.i: ; preds = %if.else.us.i.i, %for.body8.us.i.i
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%4 = phi i32 [ %3, %if.else.us.i.i ], [ 0, %for.body8.us.i.i ]
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%arrayidx36.us.i.i = getelementptr inbounds i32, i32* %c0.0103.us.i.i, i32 %c.093.us.i.i
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store i32 %4, i32* %arrayidx36.us.i.i, align 4
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%inc.us.i.i = add nsw i32 %inc.196.us.i.i, 1
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%cmp38.us.i.i = icmp sgt i32 %inc.196.us.i.i, 6
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br i1 %cmp38.us.i.i, label %if.then40.us.i.i, label %for.inc.us.i.i
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if.then40.us.i.i: ; preds = %if.end37.us.i.i
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br label %for.inc.us.i.i
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for.inc.us.i.i: ; preds = %if.then40.us.i.i, %if.end37.us.i.i
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%inc.2.us.i.i = phi i32 [ 0, %if.then40.us.i.i ], [ %inc.us.i.i, %if.end37.us.i.i ]
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%inc43.us.i.i = add nuw nsw i32 %c.093.us.i.i, 1
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%exitcond.i.i = icmp eq i32 %inc43.us.i.i, 256
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br i1 %exitcond.i.i, label %if.end48.us.i.i, label %for.body8.us.i.i
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exit.i: ; preds = %if.end48.us.i.i
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ret void
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}
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