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UpdateTestChecks: Lanai triple support
Summary:
The assembly structure most resembles the SPARC pattern:
```
.globl f6 ! -- Begin function f6
.p2align 2
.type f6,@function
f6: ! @f6
.cfi_startproc
! %bb.0:
st %fp, [--%sp]
<...>
ld -8[%fp], %fp
.Lfunc_end0:
.size f6, .Lfunc_end0-f6
.cfi_endproc
! -- End function
```
Test being affected by upcoming patch, so regenerate it.
Reviewers: RKSimon, jpienaar
Reviewed By: RKSimon
Subscribers: jyknight, fedor.sergeev, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62545
llvm-svn: 362019
This commit is contained in:
Roman Lebedev
parent
55d79c5578
commit
bf24ab9e18
@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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; Test custom lowering for 32-bit integer multiplication.
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@ -5,103 +6,191 @@
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target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
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target triple = "lanai"
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; CHECK-LABEL: f6:
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @f6(i32 inreg %a) #0 {
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; CHECK-LABEL: f6:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x1, %r3
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; CHECK-NEXT: sh %r6, 0x3, %r9
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; CHECK-NEXT: sub %r9, %r3, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, 6
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ret i32 %1
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}
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; CHECK-LABEL: f7:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r6, %rv
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define i32 @f7(i32 inreg %a) #0 {
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; CHECK-LABEL: f7:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x3, %r3
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; CHECK-NEXT: sub %r3, %r6, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, 7
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ret i32 %1
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}
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; CHECK-LABEL: f8:
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; CHECK: sh %r6, 0x3, %rv
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define i32 @f8(i32 inreg %a) #0 {
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; CHECK-LABEL: f8:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x3, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = shl nsw i32 %a, 3
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ret i32 %1
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}
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; CHECK-LABEL: f9:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: add %r{{[0-9]+}}, %r6, %rv
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define i32 @f9(i32 inreg %a) #0 {
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; CHECK-LABEL: f9:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x3, %r3
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; CHECK-NEXT: add %r3, %r6, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, 9
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ret i32 %1
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}
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; CHECK-LABEL: f10:
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @f10(i32 inreg %a) #0 {
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; CHECK-LABEL: f10:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x1, %r3
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; CHECK-NEXT: sh %r6, 0x3, %r9
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; CHECK-NEXT: add %r9, %r3, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, 10
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ret i32 %1
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}
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; CHECK-LABEL: f1280:
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; CHECK: sh %r6, 0x8, %r{{[0-9]+}}
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; CHECK: sh %r6, 0xa, %r{{[0-9]+}}
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; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @f1280(i32 inreg %a) #0 {
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; CHECK-LABEL: f1280:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x8, %r3
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; CHECK-NEXT: sh %r6, 0xa, %r9
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; CHECK-NEXT: add %r9, %r3, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, 1280
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ret i32 %1
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}
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; CHECK-LABEL: fm6:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @fm6(i32 inreg %a) #0 {
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; CHECK-LABEL: fm6:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x3, %r3
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; CHECK-NEXT: sh %r6, 0x1, %r9
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; CHECK-NEXT: sub %r9, %r3, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, -6
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ret i32 %1
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}
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; CHECK-LABEL: fm7:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r6, %r{{[0-9]+}}, %rv
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define i32 @fm7(i32 inreg %a) #0 {
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; CHECK-LABEL: fm7:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x3, %r3
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; CHECK-NEXT: sub %r6, %r3, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, -7
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ret i32 %1
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}
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; CHECK-LABEL: fm8:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @fm8(i32 inreg %a) #0 {
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; CHECK-LABEL: fm8:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x3, %r3
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; CHECK-NEXT: sub %r0, %r3, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, -8
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ret i32 %1
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}
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; CHECK-LABEL: fm9:
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; CHECK: sub %r0, %r6, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r9
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; CHECK: sub %r{{[0-9]+}}, %r9, %rv
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define i32 @fm9(i32 inreg %a) #0 {
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; CHECK-LABEL: fm9:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sub %r0, %r6, %r3
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; CHECK-NEXT: sh %r6, 0x3, %r9
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; CHECK-NEXT: sub %r3, %r9, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, -9
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ret i32 %1
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}
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; CHECK-LABEL: fm10:
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @fm10(i32 inreg %a) #0 {
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; CHECK-LABEL: fm10:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sh %r6, 0x1, %r3
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; CHECK-NEXT: sub %r0, %r3, %r3
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; CHECK-NEXT: sh %r6, 0x3, %r9
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; CHECK-NEXT: sub %r3, %r9, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul nsw i32 %a, -10
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ret i32 %1
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}
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; CHECK-LABEL: h1:
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; CHECK: __mulsi3
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define i32 @h1(i32 inreg %a) #0 {
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; CHECK-LABEL: h1:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: mov 0xaaaa0000, %r3
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; CHECK-NEXT: add %pc, 0x10, %rca
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; CHECK-NEXT: st %rca, [--%sp]
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; CHECK-NEXT: bt __mulsi3
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; CHECK-NEXT: or %r3, 0xaaab, %r7
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%1 = mul i32 %a, -1431655765
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ret i32 %1
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}
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@ -69,6 +69,13 @@ ASM_FUNCTION_RISCV_RE = re.compile(
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r'.Lfunc_end[0-9]+:\n',
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flags=(re.M | re.S))
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ASM_FUNCTION_LANAI_RE = re.compile(
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r'^_?(?P<func>[^:]+):[ \t]*!+[ \t]*@(?P=func)\n'
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r'(?:[ \t]+.cfi_startproc\n)?' # drop optional cfi noise
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r'(?P<body>.*?)\s*'
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r'.Lfunc_end[0-9]+:\n',
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flags=(re.M | re.S))
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ASM_FUNCTION_SPARC_RE = re.compile(
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r'^_?(?P<func>[^:]+):[ \t]*!+[ \t]*@(?P=func)\n'
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r'(?P<body>.*?)\s*'
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@ -186,6 +193,16 @@ def scrub_asm_riscv(asm, args):
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asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
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return asm
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def scrub_asm_lanai(asm, args):
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# Scrub runs of whitespace out of the assembly, but leave the leading
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# whitespace in place.
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asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
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# Expand the tabs used for indentation.
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asm = string.expandtabs(asm, 2)
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# Strip trailing whitespace.
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asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
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return asm
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def scrub_asm_sparc(asm, args):
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# Scrub runs of whitespace out of the assembly, but leave the leading
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# whitespace in place.
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@ -266,6 +283,7 @@ def build_function_body_dictionary_for_triple(args, raw_tool_output, triple, pre
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'powerpc64le': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
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'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
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'riscv64': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
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'lanai': (scrub_asm_lanai, ASM_FUNCTION_LANAI_RE),
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'sparc': (scrub_asm_sparc, ASM_FUNCTION_SPARC_RE),
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'sparcv9': (scrub_asm_sparc, ASM_FUNCTION_SPARC_RE),
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's390x': (scrub_asm_systemz, ASM_FUNCTION_SYSTEMZ_RE),
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