RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Code Issues Projects Releases Wiki Activity

[GlobalISel] Pointers are legal operands for G_SELECT on AArch64

Browse Source 
Differential Revision: https://reviews.llvm.org/D28805

llvm-svn: 292481
This commit is contained in:
Kristof Beyls 2017-01-19 13:32:14 +00:00
parent 8e858e78f5
commit bf2cbd3175
3 changed files with 14 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -1026,7 +1026,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
if (Ty == LLT::scalar(32)) {
CSelOpc = AArch64::CSELWr;
} else if (Ty == LLT::scalar(64)) {
} else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
CSelOpc = AArch64::CSELXr;
} else {
return false;

2
lib/Target/AArch64/AArch64LegalizerInfo.cpp
View File

@ -160,7 +160,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() {
setAction({G_BRCOND, Ty}, Legal);
// Select
for (auto Ty : {s1, s8, s16, s32, s64})
for (auto Ty : {s1, s8, s16, s32, s64, p0})
setAction({G_SELECT, Ty}, Legal);
setAction({G_SELECT, 1, s1}, Legal);

12
test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
View File

@ -2950,6 +2950,9 @@ tracksRegLiveness: true
# CHECK-NEXT: - { id: 4, class: gpr64 }
# CHECK-NEXT: - { id: 5, class: gpr64 }
# CHECK-NEXT: - { id: 6, class: gpr64 }
# CHECK-NEXT: - { id: 7, class: gpr64 }
# CHECK-NEXT: - { id: 8, class: gpr64 }
# CHECK-NEXT: - { id: 9, class: gpr64 }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -2958,12 +2961,17 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
- { id: 8, class: gpr }
- { id: 9, class: gpr }
# CHECK: body:
# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
# CHECK: %3 = CSELWr %1, %2, 1, implicit %nzcv
# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
# CHECK: %6 = CSELXr %4, %5, 1, implicit %nzcv
# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
# CHECK: %9 = CSELXr %7, %8, 1, implicit %nzcv
body: |
bb.0:
liveins: %w0, %w1, %w2
@ -2976,4 +2984,8 @@ body: |
%4(s64) = COPY %x0
%5(s64) = COPY %x1
%6(s64) = G_SELECT %0, %4, %5
%7(p0) = COPY %x0
%8(p0) = COPY %x1
%9(p0) = G_SELECT %0, %7, %8
...