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[CodeGen][SVE] CopyToReg: Split scalable EVTs that are not powers of 2
Scalable vectors cannot use 'BUILD_VECTOR', so it is necessary to
properly split and widen scalable vectors when passing them
to CopyToReg/CopyFromReg.
This functionality is added to TargetLoweringBase::getVectorTypeBreakdown().
This patch only adds support for 'splitting' scalable vectors that
are a multiple of some legal type, e.g.
<vscale x 6 x i64> -> 3 x <vscale x 2 x i64>
Reviewers: efriedma, c-rhodes
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80139
This commit is contained in:
Sander de Smalen
parent
16c9f00d4f
commit
bf414ae934
@ -955,6 +955,12 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
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unsigned NumVectorRegs = 1;
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// Scalable vectors cannot be scalarized, so splitting or widening is
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// required.
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if (VT.isScalableVector() && !isPowerOf2_32(EC.Min))
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llvm_unreachable(
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"Splitting or widening of non-power-of-2 MVTs is not implemented.");
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// FIXME: We don't support non-power-of-2-sized vectors for now.
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// Ideally we could break down into LHS/RHS like LegalizeDAG does.
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if (!isPowerOf2_32(EC.Min)) {
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@ -1418,8 +1424,34 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT
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unsigned NumVectorRegs = 1;
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// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
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// could break down into LHS/RHS like LegalizeDAG does.
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// Scalable vectors cannot be scalarized, so handle the legalisation of the
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// types like done elsewhere in SelectionDAG.
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if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.Min)) {
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LegalizeKind LK;
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EVT PartVT = VT;
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do {
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// Iterate until we've found a legal (part) type to hold VT.
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LK = getTypeConversion(Context, PartVT);
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PartVT = LK.second;
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} while (LK.first != TypeLegal);
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NumIntermediates =
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VT.getVectorElementCount().Min / PartVT.getVectorElementCount().Min;
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// FIXME: This code needs to be extended to handle more complex vector
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// breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only
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// supported cases are vectors that are broken down into equal parts
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// such as nxv6i64 -> 3 x nxv2i64.
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assert(NumIntermediates * PartVT.getVectorElementCount().Min ==
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VT.getVectorElementCount().Min &&
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"Expected an integer multiple of PartVT");
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IntermediateVT = PartVT;
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RegisterVT = getRegisterType(Context, IntermediateVT);
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return NumIntermediates;
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}
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// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
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// we could break down into LHS/RHS like LegalizeDAG does.
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if (!isPowerOf2_32(EltCnt.Min)) {
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NumVectorRegs = EltCnt.Min;
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EltCnt.Min = 1;
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312
test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
Normal file
312
test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
Normal file
@ -0,0 +1,312 @@
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
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; Test that scalable vectors that are a multiple of the legal vector size
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; can be properly broken down into part vectors.
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declare void @bar()
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;
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; Vectors twice the size
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;
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define <vscale x 32 x i8> @wide_32i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x i8> %illegal) nounwind {
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; CHECK-LABEL: wide_32i8
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 32 x i8> undef
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L2:
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ret <vscale x 32 x i8> %illegal
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}
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define <vscale x 16 x i16> @wide_16i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x i16> %illegal) nounwind {
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; CHECK-LABEL: wide_16i16
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 16 x i16> undef
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L2:
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ret <vscale x 16 x i16> %illegal
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}
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define <vscale x 8 x i32> @wide_8i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x i32> %illegal) nounwind {
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; CHECK-LABEL: wide_8i32
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 8 x i32> undef
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L2:
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ret <vscale x 8 x i32> %illegal
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}
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define <vscale x 4 x i64> @wide_4i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 4 x i64> %illegal) nounwind {
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; CHECK-LABEL: wide_4i64
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 4 x i64> undef
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L2:
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ret <vscale x 4 x i64> %illegal
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}
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define <vscale x 16 x half> @wide_16f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x half> %illegal) nounwind {
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; CHECK-LABEL: wide_16f16
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 16 x half> undef
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L2:
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ret <vscale x 16 x half> %illegal
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}
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define <vscale x 8 x float> @wide_8f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x float> %illegal) nounwind {
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; CHECK-LABEL: wide_8f32
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 8 x float> undef
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L2:
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ret <vscale x 8 x float> %illegal
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}
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define <vscale x 4 x double> @wide_4f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 4 x double> %illegal) nounwind {
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; CHECK-LABEL: wide_4f64
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 4 x double> undef
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L2:
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ret <vscale x 4 x double> %illegal
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}
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;
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; Vectors three times the size
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;
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define <vscale x 48 x i8> @wide_48i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 48 x i8> %illegal) nounwind {
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; CHECK-LABEL: wide_48i8
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 48 x i8> undef
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L2:
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ret <vscale x 48 x i8> %illegal
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}
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define <vscale x 24 x i16> @wide_24i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 24 x i16> %illegal) nounwind {
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; CHECK-LABEL: wide_24i16
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 24 x i16> undef
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L2:
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ret <vscale x 24 x i16> %illegal
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}
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define <vscale x 12 x i32> @wide_12i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 12 x i32> %illegal) nounwind {
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; CHECK-LABEL: wide_12i32
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 12 x i32> undef
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L2:
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ret <vscale x 12 x i32> %illegal
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}
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define <vscale x 6 x i64> @wide_6i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 6 x i64> %illegal) nounwind {
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; CHECK-LABEL: wide_6i64
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 6 x i64> undef
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L2:
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ret <vscale x 6 x i64> %illegal
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}
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define <vscale x 24 x half> @wide_24f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 24 x half> %illegal) nounwind {
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; CHECK-LABEL: wide_24f16
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 24 x half> undef
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L2:
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ret <vscale x 24 x half> %illegal
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}
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define <vscale x 12 x float> @wide_12f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 12 x float> %illegal) nounwind {
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; CHECK-LABEL: wide_12f32
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 12 x float> undef
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L2:
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ret <vscale x 12 x float> %illegal
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}
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define <vscale x 6 x double> @wide_6f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 6 x double> %illegal) nounwind {
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; CHECK-LABEL: wide_6f64
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 6 x double> undef
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L2:
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ret <vscale x 6 x double> %illegal
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}
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;
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; Vectors four times the size
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;
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define <vscale x 64 x i8> @wide_64i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 64 x i8> %illegal) nounwind {
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; CHECK-LABEL: wide_64i8
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: mov z3.d, z4.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 64 x i8> undef
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L2:
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ret <vscale x 64 x i8> %illegal
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}
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define <vscale x 32 x i16> @wide_32i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x i16> %illegal) nounwind {
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; CHECK-LABEL: wide_32i16
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: mov z3.d, z4.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 32 x i16> undef
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L2:
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ret <vscale x 32 x i16> %illegal
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}
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define <vscale x 16 x i32> @wide_16i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x i32> %illegal) nounwind {
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; CHECK-LABEL: wide_16i32
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: mov z3.d, z4.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 16 x i32> undef
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L2:
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ret <vscale x 16 x i32> %illegal
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}
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define <vscale x 8 x i64> @wide_8i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x i64> %illegal) nounwind {
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; CHECK-LABEL: wide_8i64
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: mov z3.d, z4.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 8 x i64> undef
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L2:
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ret <vscale x 8 x i64> %illegal
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}
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define <vscale x 32 x half> @wide_32f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x half> %illegal) nounwind {
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; CHECK-LABEL: wide_32f16
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: mov z3.d, z4.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 32 x half> undef
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L2:
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ret <vscale x 32 x half> %illegal
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}
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define <vscale x 16 x float> @wide_16f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x float> %illegal) nounwind {
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; CHECK-LABEL: wide_16f32
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: mov z3.d, z4.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 16 x float> undef
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L2:
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ret <vscale x 16 x float> %illegal
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}
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define <vscale x 8 x double> @wide_8f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x double> %illegal) nounwind {
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; CHECK-LABEL: wide_8f64
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: mov z1.d, z2.d
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; CHECK-NEXT: mov z2.d, z3.d
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; CHECK-NEXT: mov z3.d, z4.d
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; CHECK-NEXT: ret
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br i1 %b, label %L1, label %L2
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L1:
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call void @bar()
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ret <vscale x 8 x double> undef
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L2:
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ret <vscale x 8 x double> %illegal
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}
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