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[MSAN] Implement experimental vector reduction intrinsics
Implement llvm.experimental.vector.{add,mul,or,and,...}.
An IR test is included but no C test for lack of good way to
get the compiler to emit these.
Differential Revision: https://reviews.llvm.org/D82920
This commit is contained in:
Gui Andrade
parent
6a4c481801
commit
bf5a8236eb
@ -2889,6 +2889,50 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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setOriginForNaryOp(I);
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}
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// Instrument generic vector reduction intrinsics
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// by ORing together all their fields.
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void handleVectorReduceIntrinsic(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value *S = IRB.CreateOrReduce(getShadow(&I, 0));
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setShadow(&I, S);
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setOrigin(&I, getOrigin(&I, 0));
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}
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// Instrument experimental.vector.reduce.or intrinsic.
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// Valid (non-poisoned) set bits in the operand pull low the
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// corresponding shadow bits.
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void handleVectorReduceOrIntrinsic(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value *OperandShadow = getShadow(&I, 0);
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Value *OperandUnsetBits = IRB.CreateNot(I.getOperand(0));
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Value *OperandUnsetOrPoison = IRB.CreateOr(OperandUnsetBits, OperandShadow);
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// Bit N is clean if any field's bit N is 1 and unpoison
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Value *OutShadowMask = IRB.CreateAndReduce(OperandUnsetOrPoison);
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// Otherwise, it is clean if every field's bit N is unpoison
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Value *OrShadow = IRB.CreateOrReduce(OperandShadow);
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Value *S = IRB.CreateAnd(OutShadowMask, OrShadow);
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setShadow(&I, S);
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setOrigin(&I, getOrigin(&I, 0));
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}
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// Instrument experimental.vector.reduce.or intrinsic.
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// Valid (non-poisoned) unset bits in the operand pull down the
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// corresponding shadow bits.
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void handleVectorReduceAndIntrinsic(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value *OperandShadow = getShadow(&I, 0);
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Value *OperandSetOrPoison = IRB.CreateOr(I.getOperand(0), OperandShadow);
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// Bit N is clean if any field's bit N is 0 and unpoison
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Value *OutShadowMask = IRB.CreateAndReduce(OperandSetOrPoison);
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// Otherwise, it is clean if every field's bit N is unpoison
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Value *OrShadow = IRB.CreateOrReduce(OperandShadow);
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Value *S = IRB.CreateAnd(OutShadowMask, OrShadow);
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setShadow(&I, S);
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setOrigin(&I, getOrigin(&I, 0));
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}
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void handleStmxcsr(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value* Addr = I.getArgOperand(0);
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@ -3107,6 +3151,17 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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case Intrinsic::masked_load:
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handleMaskedLoad(I);
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break;
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case Intrinsic::experimental_vector_reduce_and:
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handleVectorReduceAndIntrinsic(I);
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break;
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case Intrinsic::experimental_vector_reduce_or:
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handleVectorReduceOrIntrinsic(I);
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break;
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case Intrinsic::experimental_vector_reduce_add:
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case Intrinsic::experimental_vector_reduce_xor:
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case Intrinsic::experimental_vector_reduce_mul:
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handleVectorReduceIntrinsic(I);
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break;
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case Intrinsic::x86_sse_stmxcsr:
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handleStmxcsr(I);
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break;
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68
test/Instrumentation/MemorySanitizer/experimental-reduce.ll
Normal file
68
test/Instrumentation/MemorySanitizer/experimental-reduce.ll
Normal file
@ -0,0 +1,68 @@
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; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes='module(msan-module),function(msan)' 2>&1 | \
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; RUN: FileCheck -allow-deprecated-dag-overlap -check-prefixes=CHECK,CHECK-ORIGINS %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare i32 @llvm.experimental.vector.reduce.add(<3 x i32>)
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declare i32 @llvm.experimental.vector.reduce.and(<3 x i32>)
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declare i32 @llvm.experimental.vector.reduce.or(<3 x i32>)
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; CHECK-LABEL: @reduce_add
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define i32 @reduce_add() sanitize_memory {
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; CHECK: [[P:%.*]] = inttoptr i64 0 to <3 x i32>*
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%p = inttoptr i64 0 to <3 x i32> *
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; CHECK: [[O:%.*]] = load <3 x i32>, <3 x i32>* [[P]]
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%o = load <3 x i32>, <3 x i32> *%p
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; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, <3 x i32>*
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; CHECK: [[O_ORIGIN:%.*]] = load i32, i32*
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; CHECK: [[R_SHADOW:%.*]] = call i32 @llvm.experimental.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]])
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; CHECK: [[R:%.*]] = call i32 @llvm.experimental.vector.reduce.add.v3i32(<3 x i32> [[O]])
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%r = call i32 @llvm.experimental.vector.reduce.add(<3 x i32> %o)
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; CHECK: store i32 [[R_SHADOW]], {{.*}} @__msan_retval_tls
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; CHECK: store i32 [[O_ORIGIN]], {{.*}} @__msan_retval_origin_tls
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; CHECK: ret i32 [[R]]
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ret i32 %r
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}
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; CHECK-LABEL: @reduce_and
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define i32 @reduce_and() sanitize_memory {
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; CHECK: [[P:%.*]] = inttoptr i64 0 to <3 x i32>*
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%p = inttoptr i64 0 to <3 x i32> *
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; CHECK: [[O:%.*]] = load <3 x i32>, <3 x i32>* [[P]]
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%o = load <3 x i32>, <3 x i32> *%p
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; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, <3 x i32>*
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; CHECK: [[O_ORIGIN:%.*]] = load i32, i32*
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; CHECK: [[O_SHADOW_1:%.*]] = or <3 x i32> [[O]], [[O_SHADOW]]
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; CHECK: [[O_SHADOW_2:%.*]] = call i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> [[O_SHADOW_1]]
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; CHECK: [[O_SHADOW_3:%.*]] = call i32 @llvm.experimental.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]])
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; CHECK: [[R_SHADOW:%.*]] = and i32 [[O_SHADOW_2]], [[O_SHADOW_3]]
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; CHECK: [[R:%.*]] = call i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> [[O]])
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%r = call i32 @llvm.experimental.vector.reduce.and(<3 x i32> %o)
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; CHECK: store i32 [[R_SHADOW]], {{.*}} @__msan_retval_tls
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; CHECK: store i32 [[O_ORIGIN]], {{.*}} @__msan_retval_origin_tls
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; CHECK: ret i32 [[R]]
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ret i32 %r
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}
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; CHECK-LABEL: @reduce_or
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define i32 @reduce_or() sanitize_memory {
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; CHECK: [[P:%.*]] = inttoptr i64 0 to <3 x i32>*
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%p = inttoptr i64 0 to <3 x i32> *
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; CHECK: [[O:%.*]] = load <3 x i32>, <3 x i32>* [[P]]
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%o = load <3 x i32>, <3 x i32> *%p
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; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, <3 x i32>*
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; CHECK: [[O_ORIGIN:%.*]] = load i32, i32*
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; CHECK: [[NOT_O:%.*]] = xor <3 x i32> [[O]], <i32 -1, i32 -1, i32 -1>
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; CHECK: [[O_SHADOW_1:%.*]] = or <3 x i32> [[NOT_O]], [[O_SHADOW]]
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; CHECK: [[O_SHADOW_2:%.*]] = call i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> [[O_SHADOW_1]]
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; CHECK: [[O_SHADOW_3:%.*]] = call i32 @llvm.experimental.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]])
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; CHECK: [[R_SHADOW:%.*]] = and i32 [[O_SHADOW_2]], [[O_SHADOW_3]]
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; CHECK: [[R:%.*]] = call i32 @llvm.experimental.vector.reduce.or.v3i32(<3 x i32> [[O]])
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%r = call i32 @llvm.experimental.vector.reduce.or(<3 x i32> %o)
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; CHECK: store i32 [[R_SHADOW]], {{.*}} @__msan_retval_tls
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; CHECK: store i32 [[O_ORIGIN]], {{.*}} @__msan_retval_origin_tls
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; CHECK: ret i32 [[R]]
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ret i32 %r
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}
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