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[llc] (almost) remove --print-machineinstrs

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Its effect could be achieved by
`-stop-after`,`-print-after`,`-print-after-all`. But a few tests need to
print MIR after ISel which could not be done with
`-print-after`/`-stop-after` since isel pass does not have commandline name.
That's the reason `--print-machineinstrs` is downgraded to
`--print-after-isel` in this patch. `--print-after-isel` could be
removed after we switch to new pass manager since isel pass would have a
commandline text name to use `print-after` or equivalent switches.

The motivation of this patch is to reduce tests dependency on
would-be-deprecated feature.

Reviewed By: arsenm, dsanders

Differential Revision: https://reviews.llvm.org/D83275
This commit is contained in:
Yuanfang Chen 2020-07-20 10:09:41 -07:00
parent f08273f200
commit bf8086d1c1
22 changed files with 59 additions and 138 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/CommandGuide/llc.rst
View File

@ -163,9 +163,9 @@ End-user Options
Tuning/Configuration Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. option:: --print-machineinstrs
.. option:: --print-after-isel
Print generated machine code between compilation phases (useful for debugging).
Print generated machine code after instruction selection (useful for debugging).
.. option:: --regalloc=<allocator>

2
docs/CommandGuide/lli.rst
View File

@ -165,7 +165,7 @@ CODE GENERATION OPTIONS
=simple-noitin: Simple two pass scheduling: Same as simple except using generic latency
=list-burr: Bottom-up register reduction list scheduling
=list-tdrr: Top-down register reduction list scheduling
=list-td: Top-down list scheduler -print-machineinstrs - Print generated machine code
=list-td: Top-down list scheduler
.. option:: -regalloc=allocator

15
include/llvm/CodeGen/TargetPassConfig.h
View File

@ -187,7 +187,7 @@ public:
/// Insert InsertedPassID pass after TargetPassID pass.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
bool VerifyAfter = true, bool PrintAfter = true);
bool VerifyAfter = true);
/// Allow the target to enable a specific standard pass by default.
void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
@ -319,8 +319,8 @@ public:
/// Add standard passes after a pass that has just been added. For example,
/// the MachineVerifier if it is enabled.
void addMachinePostPasses(const std::string &Banner, bool AllowPrint = true,
bool AllowVerify = true, bool AllowStrip = true);
void addMachinePostPasses(const std::string &Banner, bool AllowVerify = true,
bool AllowStrip = true);
/// Check whether or not GlobalISel should abort on error.
/// When this is disabled, GlobalISel will fall back on SDISel instead of
@ -441,21 +441,16 @@ protected:
/// Add a CodeGen pass at this point in the pipeline after checking overrides.
/// Return the pass that was added, or zero if no pass was added.
/// @p printAfter if true and adding a machine function pass add an extra
/// machine printer pass afterwards
/// @p verifyAfter if true and adding a machine function pass add an extra
/// machine verification pass afterwards.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
bool printAfter = true);
AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true);
/// Add a pass to the PassManager if that pass is supposed to be run, as
/// determined by the StartAfter and StopAfter options. Takes ownership of the
/// pass.
/// @p printAfter if true and adding a machine function pass add an extra
/// machine printer pass afterwards
/// @p verifyAfter if true and adding a machine function pass add an extra
/// machine verification pass afterwards.
void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
void addPass(Pass *P, bool verifyAfter = true);
/// addMachinePasses helper to create the target-selected or overriden
/// regalloc pass.

2
include/llvm/Target/TargetMachine.h
View File

@ -241,8 +241,6 @@ public:
Options.SupportsDebugEntryValues = Enable;
}
bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
/// Return true if unique basic block section names must be generated.

10
include/llvm/Target/TargetOptions.h
View File

@ -113,9 +113,8 @@ namespace llvm {
class TargetOptions {
public:
TargetOptions()
: PrintMachineCode(false), UnsafeFPMath(false), NoInfsFPMath(false),
NoNaNsFPMath(false), NoTrappingFPMath(true),
NoSignedZerosFPMath(false),
: UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
NoTrappingFPMath(true), NoSignedZerosFPMath(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
@ -131,11 +130,6 @@ namespace llvm {
XRayOmitFunctionIndex(false),
FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {}
/// PrintMachineCode - This flag is enabled when the -print-machineinstrs
/// option is specified on the command line, and should enable debugging
/// output from the code generator.
unsigned PrintMachineCode : 1;
/// DisableFramePointerElim - This returns true if frame pointer elimination
/// optimization should be disabled for the given machine function.
bool DisableFramePointerElim(const MachineFunction &MF) const;

2
lib/CodeGen/MachineOperand.cpp
View File

@ -1142,7 +1142,7 @@ void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
const MIRFormatter *Formatter = TII->getMIRFormatter();
// FIXME: This is not necessarily the correct MIR serialization format for
// a custom pseudo source value, but at least it allows
// -print-machineinstrs to work on a target with custom pseudo source
// MIR printing to work on a target with custom pseudo source
// values.
OS << "custom \"";
Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);

58
lib/CodeGen/TargetPassConfig.cpp
View File

@ -141,9 +141,11 @@ static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
"global-isel", cl::Hidden,
cl::desc("Enable the \"global\" instruction selector"));
static cl::opt<std::string> PrintMachineInstrs(
"print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
// first...
static cl::opt<bool>
PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
cl::desc("Print machine instrs after ISel"));
static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
"global-isel-abort", cl::Hidden,
@ -294,12 +296,11 @@ struct InsertedPass {
AnalysisID TargetPassID;
IdentifyingPassPtr InsertedPassID;
bool VerifyAfter;
bool PrintAfter;
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
bool VerifyAfter, bool PrintAfter)
bool VerifyAfter)
: TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
VerifyAfter(VerifyAfter) {}
Pass *getInsertedPass() const {
assert(InsertedPassID.isValid() && "Illegal Pass ID!");
@ -411,9 +412,6 @@ TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
if (StringRef(PrintMachineInstrs.getValue()).equals(""))
TM.Options.PrintMachineCode = true;
if (EnableIPRA.getNumOccurrences())
TM.Options.EnableIPRA = EnableIPRA;
else {
@ -437,14 +435,13 @@ CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
/// Insert InsertedPassID pass after TargetPassID.
void TargetPassConfig::insertPass(AnalysisID TargetPassID,
IdentifyingPassPtr InsertedPassID,
bool VerifyAfter, bool PrintAfter) {
bool VerifyAfter) {
assert(((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) ||
(InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!");
Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
PrintAfter);
Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter);
}
/// createPassConfig - Create a pass configuration object to be used by
@ -522,7 +519,7 @@ bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
/// a later pass or that it should stop after an earlier pass, then do not add
/// the pass. Finally, compare the current pass against the StartAfter
/// and StopAfter options and change the Started/Stopped flags accordingly.
void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
void TargetPassConfig::addPass(Pass *P, bool verifyAfter) {
assert(!Initialized && "PassConfig is immutable");
// Cache the Pass ID here in case the pass manager finds this pass is
@ -540,17 +537,16 @@ void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
addMachinePrePasses();
std::string Banner;
// Construct banner message before PM->add() as that may delete the pass.
if (AddingMachinePasses && (printAfter || verifyAfter))
if (AddingMachinePasses && verifyAfter)
Banner = std::string("After ") + std::string(P->getPassName());
PM->add(P);
if (AddingMachinePasses)
addMachinePostPasses(Banner, /*AllowPrint*/ printAfter,
/*AllowVerify*/ verifyAfter);
addMachinePostPasses(Banner, /*AllowVerify*/ verifyAfter);
// Add the passes after the pass P if there is any.
for (auto IP : Impl->InsertedPasses) {
if (IP.TargetPassID == PassID)
addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
addPass(IP.getInsertedPass(), IP.VerifyAfter);
}
} else {
delete P;
@ -570,8 +566,7 @@ void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
///
/// addPass cannot return a pointer to the pass instance because is internal the
/// PassManager and the instance we create here may already be freed.
AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
bool printAfter) {
AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter) {
IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
if (!FinalPtr.isValid())
@ -586,7 +581,7 @@ AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
llvm_unreachable("Pass ID not registered");
}
AnalysisID FinalID = P->getPassID();
addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
addPass(P, verifyAfter); // Ends the lifetime of P.
return FinalID;
}
@ -597,7 +592,7 @@ void TargetPassConfig::printAndVerify(const std::string &Banner) {
}
void TargetPassConfig::addPrintPass(const std::string &Banner) {
if (TM->shouldPrintMachineCode())
if (PrintAfterISel)
PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
}
@ -625,12 +620,9 @@ void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
}
void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
bool AllowPrint, bool AllowVerify,
bool AllowStrip) {
bool AllowVerify, bool AllowStrip) {
if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
addStripDebugPass();
if (AllowPrint)
addPrintPass(Banner);
if (AllowVerify)
addVerifyPass(Banner);
}
@ -916,20 +908,6 @@ static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
void TargetPassConfig::addMachinePasses() {
AddingMachinePasses = true;
// Insert a machine instr printer pass after the specified pass.
StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
if (!PrintMachineInstrsPassName.equals("") &&
!PrintMachineInstrsPassName.equals("option-unspecified")) {
if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
const PassRegistry *PR = PassRegistry::getPassRegistry();
const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
const char *TID = (const char *)(TPI->getTypeInfo());
const char *IID = (const char *)(IPI->getTypeInfo());
insertPass(TID, IID);
}
}
// Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) {
addMachineSSAOptimization();
@ -1000,7 +978,7 @@ void TargetPassConfig::addMachinePasses() {
// GC
if (addGCPasses()) {
if (PrintGCInfo)
addPass(createGCInfoPrinter(dbgs()), false, false);
addPass(createGCInfoPrinter(dbgs()), false);
}
// Basic block placement.

3
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -295,8 +295,7 @@ MipsTargetMachine::getTargetTransformInfo(const Function &F) {
}
// Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
// machine code is emitted.
void MipsPassConfig::addPreEmitPass() {
// Expand pseudo instructions that are sensitive to register allocation.
addPass(createMipsExpandPseudoPass());

4
test/CodeGen/AArch64/chkstk.ll
View File

@ -1,11 +1,11 @@
; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs %s -o - \
; RUN: | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
; RUN: llc -mtriple=aarch64-windows -print-machineinstrs=prologepilog %s -o - 2>&1 \
; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog \
; RUN: | FileCheck -check-prefix CHECK-REGSTATE %s
; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs -code-model=large %s -o - \
; RUN: | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
; RUN: llc -mtriple=aarch64-windows -print-machineinstrs=prologepilog -code-model=large %s -o - 2>&1 \
; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog -code-model=large \
; RUN: | FileCheck -check-prefix CHECK-REGSTATE-LARGE %s
define void @check_watermark() {

10
test/CodeGen/AArch64/max-jump-table.ll
View File

@ -1,8 +1,8 @@
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t
declare void @ext(i32, i32)

8
test/CodeGen/AArch64/min-jump-table.ll
View File

@ -1,7 +1,7 @@
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
declare void @ext(i32, i32)

2
test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=armv4t--linux-androideabi -print-machineinstrs=if-converter -o /dev/null 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=armv4t--linux-androideabi -stop-after=if-converter | FileCheck %s
; Fix a bug triggered in IfConverterTriangle when CvtBB has multiple
; predecessors.
; PR18752

2
test/CodeGen/ARM/ifcvt-branch-weight.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumbv8 -print-machineinstrs=if-converter -arm-atomic-cfg-tidy=0 -o /dev/null 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv8 -stop-after=if-converter -arm-atomic-cfg-tidy=0 | FileCheck %s
%struct.S = type { i8* (i8*)*, [1 x i8] }
define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {

2
test/CodeGen/ARM/ifcvt-iter-indbr.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -print-machineinstrs=if-converter 2>&1 | FileCheck --check-prefix=CHECK-PROB %s
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -stop-after=if-converter | FileCheck --check-prefix=CHECK-PROB %s
declare i32 @foo(i32)
declare i8* @bar(i32, i8*, i8*)

5
test/CodeGen/ARM/tail-merge-branch-weight.ll
View File

@ -1,5 +1,4 @@
; RUN: llc -mtriple=arm-apple-ios -print-machineinstrs=branch-folder \
; RUN: %s -o /dev/null 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-ios -stop-after=branch-folder | FileCheck %s
; Branch probability of tailed-merged block:
;
@ -8,11 +7,9 @@
; p(L0_L1 -> L3) = p(entry -> L0) * p(L0 -> L3) + p(entry -> L1) * p(L1 -> L3)
; = 0.2 * 0.4 + 0.8 * 0.7 = 0.64
; CHECK: # Machine code for function test0:
; CHECK: successors: %bb.{{[0-9]+}}(0x1999999a), %bb.{{[0-9]+}}(0x66666666)
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
; CHECK: # End machine code for function test0.
define i32 @test0(i32 %n, i32 %m, i32* nocapture %a, i32* nocapture %b) {
entry:

9
test/CodeGen/ARM/taildup-branch-weight.ll
View File

@ -1,8 +1,7 @@
; RUN: llc -mtriple=arm-eabi -print-machineinstrs=tailduplication -tail-dup-size=100 \
; RUN: -enable-tail-merge=false -disable-cgp %s -o /dev/null 2>&1 \
; RUN: | FileCheck %s
; RUN: llc < %s -mtriple=arm-eabi -stop-after=tailduplication -tail-dup-size=100 \
; RUN: -enable-tail-merge=false -disable-cgp | FileCheck %s
; CHECK: Machine code for function test0:
; CHECK: name: test0
; CHECK: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) {
@ -29,7 +28,7 @@ B4:
!0 = !{!"branch_weights", i32 4, i32 124}
; CHECK: Machine code for function test1:
; CHECK: name: test1
; CHECK: successors: %bb.2(0x7c000000), %bb.1(0x04000000)
@g0 = common global i32 0, align 4

27
test/CodeGen/Generic/print-machineinstrs.ll
View File

@ -1,27 +0,0 @@
; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs=branch-folder -verify-machineinstrs -o /dev/null 2>&1 \
; RUN: | FileCheck %s -check-prefix=PRINT-BRANCH-FOLD
; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs -verify-machineinstrs -o /dev/null 2>&1 \
; RUN: | FileCheck %s -check-prefix=PRINT
; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs= -verify-machineinstrs -o /dev/null 2>&1 \
; RUN: | FileCheck %s -check-prefix=PRINT
; Note: -verify-machineinstrs is used in order to make this test compatible with EXPENSIVE_CHECKS.
define i64 @foo(i64 %a, i64 %b) nounwind {
; PRINT-BRANCH-FOLD: -branch-folder -machineverifier -machineinstr-printer
; PRINT-BRANCH-FOLD: Control Flow Optimizer
; PRINT-BRANCH-FOLD-NEXT: Verify generated machine code
; PRINT-BRANCH-FOLD-NEXT: MachineFunction Printer
; PRINT-BRANCH-FOLD: Machine code for function foo:
; PRINT: -branch-folder -machineinstr-printer
; PRINT: Control Flow Optimizer
; PRINT-NEXT: MachineFunction Printer
; PRINT-NEXT: Verify generated machine code
; PRINT: Machine code for function foo:
%c = add i64 %a, %b
%d = trunc i64 %c to i32
%e = zext i32 %d to i64
ret i64 %e
}

2
test/CodeGen/Hexagon/ifcvt-edge-weight.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -print-machineinstrs=if-converter %s -o /dev/null 2>&1 | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -stop-after=if-converter < %s | FileCheck %s
; Check that the edge weights are updated correctly after if-conversion.
; CHECK: bb.3.if{{[0-9a-zA-Z.]*}}:

12
test/CodeGen/X86/llc-print-machineinstrs.mir
View File

@ -1,12 +0,0 @@
# Check that -print-machineinstrs doesn't assert when it's passed an unknown pass name.
# RUN: llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=greedy %s -o /dev/null
# RUN: not --crash llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=unknown %s -o /dev/null 2>&1 | FileCheck %s
# CHECK: LLVM ERROR: "unknown" pass is not registered.
...
---
name: fun
tracksRegLiveness: true
body: |
bb.0:
RET 0

6
test/DebugInfo/WebAssembly/dbg-value-live-interval.ll
View File

@ -1,10 +1,10 @@
; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
; FIXME: use -stop-after when MIR serialization output includes needed debug info.
; RUN: llc < %s -print-after=wasm-optimize-live-intervals 2>&1 | FileCheck %s
; CHECK: After WebAssembly Optimize Live Intervals:
; CHECK: {{.*}}After WebAssembly Optimize Live Intervals
; CHECK: bb.3.for.body.for.body_crit_edge:
; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
; CHECK: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
; CHECK: After WebAssembly Memory Intrinsic Results:
; ModuleID = 'fib.bc'
source_filename = "fib.c"

6
test/DebugInfo/WebAssembly/dbg-value-move-2.ll
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@ -1,10 +1,10 @@
; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
; FIXME: use -stop-after when MIR serialization output includes needed debug info.
; RUN: llc < %s -print-after=wasm-reg-stackify 2>&1 | FileCheck %s
; CHECK: After WebAssembly Register Stackify:
; CHECK: {{.*}}After WebAssembly Register Stackify
; CHECK: bb.2.for.body:
; CHECK: [[REG:%[0-9]+]]:i32 = TEE_I32 {{.*}} fib2.c:6:7
; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib2.c:2:13
; CHECK: After WebAssembly Register Coloring:
; ModuleID = 'fib2.bc'
; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib2.c -g -O2

6
test/DebugInfo/WebAssembly/dbg-value-move.ll
View File

@ -1,10 +1,10 @@
; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
; FIXME: use -stop-after when MIR serialization output includes needed debug info.
; RUN: llc < %s -print-after=wasm-reg-stackify 2>&1 | FileCheck %s
; CHECK: After WebAssembly Register Stackify:
; CHECK: {{.*}}After WebAssembly Register Stackify
; CHECK: bb.3.for.body.for.body_crit_edge:
; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
; CHECK: After WebAssembly Register Coloring:
; ModuleID = 'fib.bc'
; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib.c -g -O2