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[llc] (almost) remove --print-machineinstrs
Its effect could be achieved by `-stop-after`,`-print-after`,`-print-after-all`. But a few tests need to print MIR after ISel which could not be done with `-print-after`/`-stop-after` since isel pass does not have commandline name. That's the reason `--print-machineinstrs` is downgraded to `--print-after-isel` in this patch. `--print-after-isel` could be removed after we switch to new pass manager since isel pass would have a commandline text name to use `print-after` or equivalent switches. The motivation of this patch is to reduce tests dependency on would-be-deprecated feature. Reviewed By: arsenm, dsanders Differential Revision: https://reviews.llvm.org/D83275
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@ -163,9 +163,9 @@ End-user Options
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Tuning/Configuration Options
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Tuning/Configuration Options
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. option:: --print-machineinstrs
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.. option:: --print-after-isel
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Print generated machine code between compilation phases (useful for debugging).
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Print generated machine code after instruction selection (useful for debugging).
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.. option:: --regalloc=<allocator>
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.. option:: --regalloc=<allocator>
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@ -165,7 +165,7 @@ CODE GENERATION OPTIONS
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=simple-noitin: Simple two pass scheduling: Same as simple except using generic latency
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=simple-noitin: Simple two pass scheduling: Same as simple except using generic latency
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=list-burr: Bottom-up register reduction list scheduling
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=list-burr: Bottom-up register reduction list scheduling
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=list-tdrr: Top-down register reduction list scheduling
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=list-tdrr: Top-down register reduction list scheduling
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=list-td: Top-down list scheduler -print-machineinstrs - Print generated machine code
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=list-td: Top-down list scheduler
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.. option:: -regalloc=allocator
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.. option:: -regalloc=allocator
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@ -187,7 +187,7 @@ public:
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/// Insert InsertedPassID pass after TargetPassID pass.
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/// Insert InsertedPassID pass after TargetPassID pass.
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void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
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void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
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bool VerifyAfter = true, bool PrintAfter = true);
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bool VerifyAfter = true);
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/// Allow the target to enable a specific standard pass by default.
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/// Allow the target to enable a specific standard pass by default.
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void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
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void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
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@ -319,8 +319,8 @@ public:
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/// Add standard passes after a pass that has just been added. For example,
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/// Add standard passes after a pass that has just been added. For example,
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/// the MachineVerifier if it is enabled.
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/// the MachineVerifier if it is enabled.
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void addMachinePostPasses(const std::string &Banner, bool AllowPrint = true,
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void addMachinePostPasses(const std::string &Banner, bool AllowVerify = true,
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bool AllowVerify = true, bool AllowStrip = true);
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bool AllowStrip = true);
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/// Check whether or not GlobalISel should abort on error.
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/// Check whether or not GlobalISel should abort on error.
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/// When this is disabled, GlobalISel will fall back on SDISel instead of
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/// When this is disabled, GlobalISel will fall back on SDISel instead of
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@ -441,21 +441,16 @@ protected:
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/// Add a CodeGen pass at this point in the pipeline after checking overrides.
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/// Add a CodeGen pass at this point in the pipeline after checking overrides.
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/// Return the pass that was added, or zero if no pass was added.
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/// Return the pass that was added, or zero if no pass was added.
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/// @p printAfter if true and adding a machine function pass add an extra
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/// machine printer pass afterwards
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/// @p verifyAfter if true and adding a machine function pass add an extra
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/// @p verifyAfter if true and adding a machine function pass add an extra
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/// machine verification pass afterwards.
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/// machine verification pass afterwards.
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AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
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AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true);
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bool printAfter = true);
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/// Add a pass to the PassManager if that pass is supposed to be run, as
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/// Add a pass to the PassManager if that pass is supposed to be run, as
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/// determined by the StartAfter and StopAfter options. Takes ownership of the
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/// determined by the StartAfter and StopAfter options. Takes ownership of the
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/// pass.
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/// pass.
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/// @p printAfter if true and adding a machine function pass add an extra
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/// machine printer pass afterwards
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/// @p verifyAfter if true and adding a machine function pass add an extra
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/// @p verifyAfter if true and adding a machine function pass add an extra
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/// machine verification pass afterwards.
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/// machine verification pass afterwards.
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void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
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void addPass(Pass *P, bool verifyAfter = true);
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/// addMachinePasses helper to create the target-selected or overriden
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/// addMachinePasses helper to create the target-selected or overriden
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/// regalloc pass.
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/// regalloc pass.
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@ -241,8 +241,6 @@ public:
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Options.SupportsDebugEntryValues = Enable;
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Options.SupportsDebugEntryValues = Enable;
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}
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}
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bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
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bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
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bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
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/// Return true if unique basic block section names must be generated.
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/// Return true if unique basic block section names must be generated.
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@ -113,9 +113,8 @@ namespace llvm {
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class TargetOptions {
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class TargetOptions {
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public:
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public:
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TargetOptions()
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TargetOptions()
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: PrintMachineCode(false), UnsafeFPMath(false), NoInfsFPMath(false),
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: UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
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NoNaNsFPMath(false), NoTrappingFPMath(true),
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NoTrappingFPMath(true), NoSignedZerosFPMath(false),
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NoSignedZerosFPMath(false),
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HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
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HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
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GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
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GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
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EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
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EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
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@ -131,11 +130,6 @@ namespace llvm {
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XRayOmitFunctionIndex(false),
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XRayOmitFunctionIndex(false),
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FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {}
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FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {}
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/// PrintMachineCode - This flag is enabled when the -print-machineinstrs
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/// option is specified on the command line, and should enable debugging
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/// output from the code generator.
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unsigned PrintMachineCode : 1;
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/// DisableFramePointerElim - This returns true if frame pointer elimination
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/// DisableFramePointerElim - This returns true if frame pointer elimination
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/// optimization should be disabled for the given machine function.
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/// optimization should be disabled for the given machine function.
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bool DisableFramePointerElim(const MachineFunction &MF) const;
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bool DisableFramePointerElim(const MachineFunction &MF) const;
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@ -1142,7 +1142,7 @@ void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
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const MIRFormatter *Formatter = TII->getMIRFormatter();
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const MIRFormatter *Formatter = TII->getMIRFormatter();
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// FIXME: This is not necessarily the correct MIR serialization format for
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// FIXME: This is not necessarily the correct MIR serialization format for
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// a custom pseudo source value, but at least it allows
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// a custom pseudo source value, but at least it allows
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// -print-machineinstrs to work on a target with custom pseudo source
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// MIR printing to work on a target with custom pseudo source
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// values.
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// values.
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OS << "custom \"";
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OS << "custom \"";
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Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
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Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
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@ -141,9 +141,11 @@ static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
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"global-isel", cl::Hidden,
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"global-isel", cl::Hidden,
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cl::desc("Enable the \"global\" instruction selector"));
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cl::desc("Enable the \"global\" instruction selector"));
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static cl::opt<std::string> PrintMachineInstrs(
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// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
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"print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
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// first...
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cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
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static cl::opt<bool>
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PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
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cl::desc("Print machine instrs after ISel"));
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static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
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static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
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"global-isel-abort", cl::Hidden,
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"global-isel-abort", cl::Hidden,
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@ -294,12 +296,11 @@ struct InsertedPass {
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AnalysisID TargetPassID;
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AnalysisID TargetPassID;
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IdentifyingPassPtr InsertedPassID;
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IdentifyingPassPtr InsertedPassID;
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bool VerifyAfter;
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bool VerifyAfter;
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bool PrintAfter;
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InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
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InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
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bool VerifyAfter, bool PrintAfter)
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bool VerifyAfter)
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: TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
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: TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
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VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
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VerifyAfter(VerifyAfter) {}
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Pass *getInsertedPass() const {
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Pass *getInsertedPass() const {
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assert(InsertedPassID.isValid() && "Illegal Pass ID!");
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assert(InsertedPassID.isValid() && "Illegal Pass ID!");
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@ -411,9 +412,6 @@ TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
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initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
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initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
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initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
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initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
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if (StringRef(PrintMachineInstrs.getValue()).equals(""))
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TM.Options.PrintMachineCode = true;
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if (EnableIPRA.getNumOccurrences())
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if (EnableIPRA.getNumOccurrences())
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TM.Options.EnableIPRA = EnableIPRA;
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TM.Options.EnableIPRA = EnableIPRA;
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else {
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else {
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@ -437,14 +435,13 @@ CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
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/// Insert InsertedPassID pass after TargetPassID.
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/// Insert InsertedPassID pass after TargetPassID.
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void TargetPassConfig::insertPass(AnalysisID TargetPassID,
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void TargetPassConfig::insertPass(AnalysisID TargetPassID,
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IdentifyingPassPtr InsertedPassID,
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IdentifyingPassPtr InsertedPassID,
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bool VerifyAfter, bool PrintAfter) {
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bool VerifyAfter) {
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assert(((!InsertedPassID.isInstance() &&
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assert(((!InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getID()) ||
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TargetPassID != InsertedPassID.getID()) ||
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(InsertedPassID.isInstance() &&
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(InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
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TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
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"Insert a pass after itself!");
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"Insert a pass after itself!");
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Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
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Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter);
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PrintAfter);
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}
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}
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/// createPassConfig - Create a pass configuration object to be used by
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/// createPassConfig - Create a pass configuration object to be used by
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@ -522,7 +519,7 @@ bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
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/// a later pass or that it should stop after an earlier pass, then do not add
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/// a later pass or that it should stop after an earlier pass, then do not add
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/// the pass. Finally, compare the current pass against the StartAfter
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/// the pass. Finally, compare the current pass against the StartAfter
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/// and StopAfter options and change the Started/Stopped flags accordingly.
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/// and StopAfter options and change the Started/Stopped flags accordingly.
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void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
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void TargetPassConfig::addPass(Pass *P, bool verifyAfter) {
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assert(!Initialized && "PassConfig is immutable");
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assert(!Initialized && "PassConfig is immutable");
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// Cache the Pass ID here in case the pass manager finds this pass is
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// Cache the Pass ID here in case the pass manager finds this pass is
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@ -540,17 +537,16 @@ void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
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addMachinePrePasses();
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addMachinePrePasses();
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std::string Banner;
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std::string Banner;
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// Construct banner message before PM->add() as that may delete the pass.
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// Construct banner message before PM->add() as that may delete the pass.
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if (AddingMachinePasses && (printAfter || verifyAfter))
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if (AddingMachinePasses && verifyAfter)
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Banner = std::string("After ") + std::string(P->getPassName());
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Banner = std::string("After ") + std::string(P->getPassName());
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PM->add(P);
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PM->add(P);
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if (AddingMachinePasses)
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if (AddingMachinePasses)
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addMachinePostPasses(Banner, /*AllowPrint*/ printAfter,
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addMachinePostPasses(Banner, /*AllowVerify*/ verifyAfter);
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/*AllowVerify*/ verifyAfter);
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// Add the passes after the pass P if there is any.
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// Add the passes after the pass P if there is any.
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for (auto IP : Impl->InsertedPasses) {
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for (auto IP : Impl->InsertedPasses) {
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if (IP.TargetPassID == PassID)
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if (IP.TargetPassID == PassID)
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addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
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addPass(IP.getInsertedPass(), IP.VerifyAfter);
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}
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}
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} else {
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} else {
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delete P;
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delete P;
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@ -570,8 +566,7 @@ void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
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///
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///
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/// addPass cannot return a pointer to the pass instance because is internal the
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/// addPass cannot return a pointer to the pass instance because is internal the
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/// PassManager and the instance we create here may already be freed.
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/// PassManager and the instance we create here may already be freed.
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AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
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AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter) {
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bool printAfter) {
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IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
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IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
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IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
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IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
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if (!FinalPtr.isValid())
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if (!FinalPtr.isValid())
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@ -586,7 +581,7 @@ AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
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llvm_unreachable("Pass ID not registered");
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llvm_unreachable("Pass ID not registered");
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}
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}
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AnalysisID FinalID = P->getPassID();
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AnalysisID FinalID = P->getPassID();
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addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
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addPass(P, verifyAfter); // Ends the lifetime of P.
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return FinalID;
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return FinalID;
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}
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}
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@ -597,7 +592,7 @@ void TargetPassConfig::printAndVerify(const std::string &Banner) {
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}
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}
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void TargetPassConfig::addPrintPass(const std::string &Banner) {
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void TargetPassConfig::addPrintPass(const std::string &Banner) {
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if (TM->shouldPrintMachineCode())
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if (PrintAfterISel)
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PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
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PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
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}
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}
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@ -625,12 +620,9 @@ void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
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}
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}
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void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
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void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
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bool AllowPrint, bool AllowVerify,
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bool AllowVerify, bool AllowStrip) {
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bool AllowStrip) {
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if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
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if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
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addStripDebugPass();
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addStripDebugPass();
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if (AllowPrint)
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addPrintPass(Banner);
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if (AllowVerify)
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if (AllowVerify)
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addVerifyPass(Banner);
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addVerifyPass(Banner);
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}
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}
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@ -916,20 +908,6 @@ static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
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void TargetPassConfig::addMachinePasses() {
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void TargetPassConfig::addMachinePasses() {
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AddingMachinePasses = true;
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AddingMachinePasses = true;
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// Insert a machine instr printer pass after the specified pass.
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StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
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if (!PrintMachineInstrsPassName.equals("") &&
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!PrintMachineInstrsPassName.equals("option-unspecified")) {
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if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
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const PassRegistry *PR = PassRegistry::getPassRegistry();
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const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
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assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
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const char *TID = (const char *)(TPI->getTypeInfo());
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const char *IID = (const char *)(IPI->getTypeInfo());
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insertPass(TID, IID);
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}
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}
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// Add passes that optimize machine instructions in SSA form.
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// Add passes that optimize machine instructions in SSA form.
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if (getOptLevel() != CodeGenOpt::None) {
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if (getOptLevel() != CodeGenOpt::None) {
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addMachineSSAOptimization();
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addMachineSSAOptimization();
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@ -1000,7 +978,7 @@ void TargetPassConfig::addMachinePasses() {
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// GC
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// GC
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if (addGCPasses()) {
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if (addGCPasses()) {
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if (PrintGCInfo)
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if (PrintGCInfo)
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addPass(createGCInfoPrinter(dbgs()), false, false);
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addPass(createGCInfoPrinter(dbgs()), false);
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}
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}
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// Basic block placement.
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// Basic block placement.
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@ -295,8 +295,7 @@ MipsTargetMachine::getTargetTransformInfo(const Function &F) {
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}
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}
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// Implemented by targets that want to run passes immediately before
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// machine code is emitted.
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// print out the code after the passes.
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void MipsPassConfig::addPreEmitPass() {
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void MipsPassConfig::addPreEmitPass() {
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// Expand pseudo instructions that are sensitive to register allocation.
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// Expand pseudo instructions that are sensitive to register allocation.
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addPass(createMipsExpandPseudoPass());
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addPass(createMipsExpandPseudoPass());
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@ -1,11 +1,11 @@
|
|||||||
; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs %s -o - \
|
; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs %s -o - \
|
||||||
; RUN: | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
|
; RUN: | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
|
||||||
; RUN: llc -mtriple=aarch64-windows -print-machineinstrs=prologepilog %s -o - 2>&1 \
|
; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog \
|
||||||
; RUN: | FileCheck -check-prefix CHECK-REGSTATE %s
|
; RUN: | FileCheck -check-prefix CHECK-REGSTATE %s
|
||||||
|
|
||||||
; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs -code-model=large %s -o - \
|
; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs -code-model=large %s -o - \
|
||||||
; RUN: | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
|
; RUN: | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
|
||||||
; RUN: llc -mtriple=aarch64-windows -print-machineinstrs=prologepilog -code-model=large %s -o - 2>&1 \
|
; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog -code-model=large \
|
||||||
; RUN: | FileCheck -check-prefix CHECK-REGSTATE-LARGE %s
|
; RUN: | FileCheck -check-prefix CHECK-REGSTATE-LARGE %s
|
||||||
|
|
||||||
define void @check_watermark() {
|
define void @check_watermark() {
|
||||||
|
@ -1,8 +1,8 @@
|
|||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
|
||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
|
||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
|
||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t
|
||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t
|
||||||
|
|
||||||
declare void @ext(i32, i32)
|
declare void @ext(i32, i32)
|
||||||
|
|
||||||
|
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t
|
||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2 < %t
|
||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t
|
||||||
; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
|
; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t
|
||||||
|
|
||||||
declare void @ext(i32, i32)
|
declare void @ext(i32, i32)
|
||||||
|
|
||||||
|
@ -1,4 +1,4 @@
|
|||||||
; RUN: llc < %s -mtriple=armv4t--linux-androideabi -print-machineinstrs=if-converter -o /dev/null 2>&1 | FileCheck %s
|
; RUN: llc < %s -mtriple=armv4t--linux-androideabi -stop-after=if-converter | FileCheck %s
|
||||||
; Fix a bug triggered in IfConverterTriangle when CvtBB has multiple
|
; Fix a bug triggered in IfConverterTriangle when CvtBB has multiple
|
||||||
; predecessors.
|
; predecessors.
|
||||||
; PR18752
|
; PR18752
|
||||||
|
@ -1,4 +1,4 @@
|
|||||||
; RUN: llc < %s -mtriple=thumbv8 -print-machineinstrs=if-converter -arm-atomic-cfg-tidy=0 -o /dev/null 2>&1 | FileCheck %s
|
; RUN: llc < %s -mtriple=thumbv8 -stop-after=if-converter -arm-atomic-cfg-tidy=0 | FileCheck %s
|
||||||
|
|
||||||
%struct.S = type { i8* (i8*)*, [1 x i8] }
|
%struct.S = type { i8* (i8*)*, [1 x i8] }
|
||||||
define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
|
define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s
|
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s
|
||||||
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -print-machineinstrs=if-converter 2>&1 | FileCheck --check-prefix=CHECK-PROB %s
|
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -stop-after=if-converter | FileCheck --check-prefix=CHECK-PROB %s
|
||||||
|
|
||||||
declare i32 @foo(i32)
|
declare i32 @foo(i32)
|
||||||
declare i8* @bar(i32, i8*, i8*)
|
declare i8* @bar(i32, i8*, i8*)
|
||||||
|
@ -1,5 +1,4 @@
|
|||||||
; RUN: llc -mtriple=arm-apple-ios -print-machineinstrs=branch-folder \
|
; RUN: llc < %s -mtriple=arm-apple-ios -stop-after=branch-folder | FileCheck %s
|
||||||
; RUN: %s -o /dev/null 2>&1 | FileCheck %s
|
|
||||||
|
|
||||||
; Branch probability of tailed-merged block:
|
; Branch probability of tailed-merged block:
|
||||||
;
|
;
|
||||||
@ -8,11 +7,9 @@
|
|||||||
; p(L0_L1 -> L3) = p(entry -> L0) * p(L0 -> L3) + p(entry -> L1) * p(L1 -> L3)
|
; p(L0_L1 -> L3) = p(entry -> L0) * p(L0 -> L3) + p(entry -> L1) * p(L1 -> L3)
|
||||||
; = 0.2 * 0.4 + 0.8 * 0.7 = 0.64
|
; = 0.2 * 0.4 + 0.8 * 0.7 = 0.64
|
||||||
|
|
||||||
; CHECK: # Machine code for function test0:
|
|
||||||
; CHECK: successors: %bb.{{[0-9]+}}(0x1999999a), %bb.{{[0-9]+}}(0x66666666)
|
; CHECK: successors: %bb.{{[0-9]+}}(0x1999999a), %bb.{{[0-9]+}}(0x66666666)
|
||||||
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
|
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
|
||||||
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
|
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
|
||||||
; CHECK: # End machine code for function test0.
|
|
||||||
|
|
||||||
define i32 @test0(i32 %n, i32 %m, i32* nocapture %a, i32* nocapture %b) {
|
define i32 @test0(i32 %n, i32 %m, i32* nocapture %a, i32* nocapture %b) {
|
||||||
entry:
|
entry:
|
||||||
|
@ -1,8 +1,7 @@
|
|||||||
; RUN: llc -mtriple=arm-eabi -print-machineinstrs=tailduplication -tail-dup-size=100 \
|
; RUN: llc < %s -mtriple=arm-eabi -stop-after=tailduplication -tail-dup-size=100 \
|
||||||
; RUN: -enable-tail-merge=false -disable-cgp %s -o /dev/null 2>&1 \
|
; RUN: -enable-tail-merge=false -disable-cgp | FileCheck %s
|
||||||
; RUN: | FileCheck %s
|
|
||||||
|
|
||||||
; CHECK: Machine code for function test0:
|
; CHECK: name: test0
|
||||||
; CHECK: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
|
; CHECK: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
|
||||||
|
|
||||||
define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) {
|
define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) {
|
||||||
@ -29,7 +28,7 @@ B4:
|
|||||||
|
|
||||||
!0 = !{!"branch_weights", i32 4, i32 124}
|
!0 = !{!"branch_weights", i32 4, i32 124}
|
||||||
|
|
||||||
; CHECK: Machine code for function test1:
|
; CHECK: name: test1
|
||||||
; CHECK: successors: %bb.2(0x7c000000), %bb.1(0x04000000)
|
; CHECK: successors: %bb.2(0x7c000000), %bb.1(0x04000000)
|
||||||
|
|
||||||
@g0 = common global i32 0, align 4
|
@g0 = common global i32 0, align 4
|
||||||
|
@ -1,27 +0,0 @@
|
|||||||
; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs=branch-folder -verify-machineinstrs -o /dev/null 2>&1 \
|
|
||||||
; RUN: | FileCheck %s -check-prefix=PRINT-BRANCH-FOLD
|
|
||||||
; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs -verify-machineinstrs -o /dev/null 2>&1 \
|
|
||||||
; RUN: | FileCheck %s -check-prefix=PRINT
|
|
||||||
; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs= -verify-machineinstrs -o /dev/null 2>&1 \
|
|
||||||
; RUN: | FileCheck %s -check-prefix=PRINT
|
|
||||||
|
|
||||||
; Note: -verify-machineinstrs is used in order to make this test compatible with EXPENSIVE_CHECKS.
|
|
||||||
|
|
||||||
define i64 @foo(i64 %a, i64 %b) nounwind {
|
|
||||||
; PRINT-BRANCH-FOLD: -branch-folder -machineverifier -machineinstr-printer
|
|
||||||
; PRINT-BRANCH-FOLD: Control Flow Optimizer
|
|
||||||
; PRINT-BRANCH-FOLD-NEXT: Verify generated machine code
|
|
||||||
; PRINT-BRANCH-FOLD-NEXT: MachineFunction Printer
|
|
||||||
; PRINT-BRANCH-FOLD: Machine code for function foo:
|
|
||||||
|
|
||||||
; PRINT: -branch-folder -machineinstr-printer
|
|
||||||
; PRINT: Control Flow Optimizer
|
|
||||||
; PRINT-NEXT: MachineFunction Printer
|
|
||||||
; PRINT-NEXT: Verify generated machine code
|
|
||||||
; PRINT: Machine code for function foo:
|
|
||||||
|
|
||||||
%c = add i64 %a, %b
|
|
||||||
%d = trunc i64 %c to i32
|
|
||||||
%e = zext i32 %d to i64
|
|
||||||
ret i64 %e
|
|
||||||
}
|
|
@ -1,4 +1,4 @@
|
|||||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -print-machineinstrs=if-converter %s -o /dev/null 2>&1 | FileCheck %s
|
; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -stop-after=if-converter < %s | FileCheck %s
|
||||||
; Check that the edge weights are updated correctly after if-conversion.
|
; Check that the edge weights are updated correctly after if-conversion.
|
||||||
|
|
||||||
; CHECK: bb.3.if{{[0-9a-zA-Z.]*}}:
|
; CHECK: bb.3.if{{[0-9a-zA-Z.]*}}:
|
||||||
|
@ -1,12 +0,0 @@
|
|||||||
# Check that -print-machineinstrs doesn't assert when it's passed an unknown pass name.
|
|
||||||
# RUN: llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=greedy %s -o /dev/null
|
|
||||||
# RUN: not --crash llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=unknown %s -o /dev/null 2>&1 | FileCheck %s
|
|
||||||
# CHECK: LLVM ERROR: "unknown" pass is not registered.
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: fun
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.0:
|
|
||||||
RET 0
|
|
@ -1,10 +1,10 @@
|
|||||||
; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
|
; FIXME: use -stop-after when MIR serialization output includes needed debug info.
|
||||||
|
; RUN: llc < %s -print-after=wasm-optimize-live-intervals 2>&1 | FileCheck %s
|
||||||
|
|
||||||
; CHECK: After WebAssembly Optimize Live Intervals:
|
; CHECK: {{.*}}After WebAssembly Optimize Live Intervals
|
||||||
; CHECK: bb.3.for.body.for.body_crit_edge:
|
; CHECK: bb.3.for.body.for.body_crit_edge:
|
||||||
; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
|
; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
|
||||||
; CHECK: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
|
; CHECK: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
|
||||||
; CHECK: After WebAssembly Memory Intrinsic Results:
|
|
||||||
|
|
||||||
; ModuleID = 'fib.bc'
|
; ModuleID = 'fib.bc'
|
||||||
source_filename = "fib.c"
|
source_filename = "fib.c"
|
||||||
|
@ -1,10 +1,10 @@
|
|||||||
; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
|
; FIXME: use -stop-after when MIR serialization output includes needed debug info.
|
||||||
|
; RUN: llc < %s -print-after=wasm-reg-stackify 2>&1 | FileCheck %s
|
||||||
|
|
||||||
; CHECK: After WebAssembly Register Stackify:
|
; CHECK: {{.*}}After WebAssembly Register Stackify
|
||||||
; CHECK: bb.2.for.body:
|
; CHECK: bb.2.for.body:
|
||||||
; CHECK: [[REG:%[0-9]+]]:i32 = TEE_I32 {{.*}} fib2.c:6:7
|
; CHECK: [[REG:%[0-9]+]]:i32 = TEE_I32 {{.*}} fib2.c:6:7
|
||||||
; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib2.c:2:13
|
; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib2.c:2:13
|
||||||
; CHECK: After WebAssembly Register Coloring:
|
|
||||||
|
|
||||||
; ModuleID = 'fib2.bc'
|
; ModuleID = 'fib2.bc'
|
||||||
; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib2.c -g -O2
|
; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib2.c -g -O2
|
||||||
|
@ -1,10 +1,10 @@
|
|||||||
; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
|
; FIXME: use -stop-after when MIR serialization output includes needed debug info.
|
||||||
|
; RUN: llc < %s -print-after=wasm-reg-stackify 2>&1 | FileCheck %s
|
||||||
|
|
||||||
; CHECK: After WebAssembly Register Stackify:
|
; CHECK: {{.*}}After WebAssembly Register Stackify
|
||||||
; CHECK: bb.3.for.body.for.body_crit_edge:
|
; CHECK: bb.3.for.body.for.body_crit_edge:
|
||||||
; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
|
; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
|
||||||
; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
|
; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
|
||||||
; CHECK: After WebAssembly Register Coloring:
|
|
||||||
|
|
||||||
; ModuleID = 'fib.bc'
|
; ModuleID = 'fib.bc'
|
||||||
; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib.c -g -O2
|
; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib.c -g -O2
|
||||||
|
Loading…
Reference in New Issue
Block a user