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R600: Factorize Fetch size limit inside AMDGPUSubTarget

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llvm-svn: 182122
This commit is contained in:
Vincent Lejeune 2013-05-17 16:49:55 +00:00
parent d39a89783b
commit bf991c018d
4 changed files with 13 additions and 13 deletions
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5
lib/Target/R600/AMDGPUSubtarget.cpp
View File

@ -37,6 +37,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
ParseSubtargetFeatures(GPU, FS);
DevName = GPU;
Device = AMDGPUDeviceInfo::getDeviceFromName(DevName, this, Is64bit);
TexVTXClauseSize = (Device->getGeneration() >= AMDGPUDeviceInfo::HD4XXX)?16:8;
}
AMDGPUSubtarget::~AMDGPUSubtarget() {
@ -57,6 +58,10 @@ bool
AMDGPUSubtarget::hasVertexCache() const {
return HasVertexCache;
}
short
AMDGPUSubtarget::getTexVTXClauseSize() const {
return TexVTXClauseSize;
}
bool
AMDGPUSubtarget::isTargetELF() const {
return false;

2
lib/Target/R600/AMDGPUSubtarget.h
View File

@ -37,6 +37,7 @@ private:
bool DumpCode;
bool R600ALUInst;
bool HasVertexCache;
short TexVTXClauseSize;
InstrItineraryData InstrItins;
@ -50,6 +51,7 @@ public:
bool isOverride(AMDGPUDeviceInfo::Caps) const;
bool is64bit() const;
bool hasVertexCache() const;
short getTexVTXClauseSize() const;
// Helper functions to simplify if statements
bool isTargetELF() const;

7
lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@ -148,7 +148,7 @@ private:
for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
if (IsTrivialInst(I))
continue;
if (AluInstCount > MaxFetchInst)
if (AluInstCount >= MaxFetchInst)
break;
if ((IsTex && !TII->usesTextureCache(I)) ||
(!IsTex && !TII->usesVertexCache(I)))
@ -316,10 +316,7 @@ public:
TRI(TII->getRegisterInfo()),
ST(tm.getSubtarget<AMDGPUSubtarget>()) {
const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX)
MaxFetchInst = 8;
else
MaxFetchInst = 16;
MaxFetchInst = ST.getTexVTXClauseSize();
}
virtual bool runOnMachineFunction(MachineFunction &MF) {

12
lib/Target/R600/R600MachineScheduler.cpp
View File

@ -41,11 +41,7 @@ void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD5XXX) {
InstKindLimit[IDFetch] = 7; // 8 minus 1 for security
} else {
InstKindLimit[IDFetch] = 15; // 16 minus 1 for security
}
InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
}
void R600SchedStrategy::MoveUnits(ReadyQueue *QSrc, ReadyQueue *QDst)
@ -67,9 +63,9 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
// check if we might want to switch current clause type
bool AllowSwitchToAlu = (CurInstKind == IDOther) ||
(CurEmitted > InstKindLimit[CurInstKind]) ||
(CurEmitted >= InstKindLimit[CurInstKind]) ||
(Available[CurInstKind]->empty());
bool AllowSwitchFromAlu = (CurEmitted > InstKindLimit[CurInstKind]) &&
bool AllowSwitchFromAlu = (CurEmitted >= InstKindLimit[CurInstKind]) &&
(!Available[IDFetch]->empty() || !Available[IDOther]->empty());
if ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
@ -77,7 +73,7 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
// try to pick ALU
SU = pickAlu();
if (SU) {
if (CurEmitted > InstKindLimit[IDAlu])
if (CurEmitted >= InstKindLimit[IDAlu])
CurEmitted = 0;
NextInstKind = IDAlu;
}