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[X86] Split VRNDSCALE/VREDUCE/VGETMANT/VRANGE ISD nodes into versions with and without the rounding operand. NFCI
I want to reuse the VRNDSCALE node for the legacy SSE rounding intrinsics so that those intrinsics can use EVEX instructions. All of these nodes share tablegen multiclasses so I split them all so that they all remain similar in their implementations. llvm-svn: 318007
This commit is contained in:
Craig Topper
parent
8743ca93c4
commit
bff032a8e3
@ -19767,14 +19767,36 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SDValue passThru = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
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if (IntrWithRoundingModeOpcode != 0) {
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SDValue Rnd = Op.getOperand(5);
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if (!isRoundModeCurDirection(Rnd))
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// There are 2 kinds of intrinsics in this group:
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// (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
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// (2) With rounding mode and sae - 7 operands.
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bool HasRounding = IntrWithRoundingModeOpcode != 0;
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if (Op.getNumOperands() == (5 + HasRounding)) {
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if (HasRounding) {
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SDValue Rnd = Op.getOperand(5);
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if (!isRoundModeCurDirection(Rnd))
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return getScalarMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
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dl, VT, Src1, Src2, Rnd),
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Mask, passThru, Subtarget, DAG);
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}
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
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Src2),
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Mask, passThru, Subtarget, DAG);
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}
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assert(Op.getNumOperands() == (6 + HasRounding) &&
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"Unexpected intrinsic form");
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SDValue RoundingMode = Op.getOperand(5);
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if (HasRounding) {
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SDValue Sae = Op.getOperand(6);
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if (!isRoundModeCurDirection(Sae))
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return getScalarMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
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dl, VT, Src1, Src2, Rnd),
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dl, VT, Src1, Src2,
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RoundingMode, Sae),
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Mask, passThru, Subtarget, DAG);
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}
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
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Src2, RoundingMode),
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Mask, passThru, Subtarget, DAG);
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}
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case INTR_TYPE_SCALAR_MASK_RM: {
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@ -19843,16 +19865,23 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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Src1, Src2, Rnd),
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Mask, PassThru, Subtarget, DAG);
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}
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case INTR_TYPE_3OP_SCALAR_MASK_RM: {
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case INTR_TYPE_3OP_SCALAR_MASK: {
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SDValue Src1 = Op.getOperand(1);
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SDValue Src2 = Op.getOperand(2);
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SDValue Src3 = Op.getOperand(3);
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SDValue PassThru = Op.getOperand(4);
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SDValue Mask = Op.getOperand(5);
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SDValue Sae = Op.getOperand(6);
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unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
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if (IntrWithRoundingModeOpcode != 0) {
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SDValue Rnd = Op.getOperand(6);
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if (!isRoundModeCurDirection(Rnd))
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return getScalarMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
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dl, VT, Src1, Src2, Src3, Rnd),
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Mask, PassThru, Subtarget, DAG);
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}
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
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Src2, Src3, Sae),
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Src2, Src3),
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Mask, PassThru, Subtarget, DAG);
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}
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case INTR_TYPE_3OP_MASK_RM: {
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@ -25052,7 +25081,9 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
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case X86ISD::VFIXUPIMMS: return "X86ISD::VFIXUPIMMS";
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case X86ISD::VRANGE: return "X86ISD::VRANGE";
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case X86ISD::VRANGE_RND: return "X86ISD::VRANGE_RND";
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case X86ISD::VRANGES: return "X86ISD::VRANGES";
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case X86ISD::VRANGES_RND: return "X86ISD::VRANGES_RND";
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case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
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case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
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case X86ISD::PSADBW: return "X86ISD::PSADBW";
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@ -25103,11 +25134,17 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VPMADD52H: return "X86ISD::VPMADD52H";
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case X86ISD::VPMADD52L: return "X86ISD::VPMADD52L";
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case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
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case X86ISD::VRNDSCALE_RND: return "X86ISD::VRNDSCALE_RND";
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case X86ISD::VRNDSCALES: return "X86ISD::VRNDSCALES";
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case X86ISD::VRNDSCALES_RND: return "X86ISD::VRNDSCALES_RND";
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case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
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case X86ISD::VREDUCE_RND: return "X86ISD::VREDUCE_RND";
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case X86ISD::VREDUCES: return "X86ISD::VREDUCES";
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case X86ISD::VREDUCES_RND: return "X86ISD::VREDUCES_RND";
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case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
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case X86ISD::VGETMANT_RND: return "X86ISD::VGETMANT_RND";
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case X86ISD::VGETMANTS: return "X86ISD::VGETMANTS";
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case X86ISD::VGETMANTS_RND: return "X86ISD::VGETMANTS_RND";
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case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
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case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
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case X86ISD::XTEST: return "X86ISD::XTEST";
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@ -214,7 +214,7 @@ namespace llvm {
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// FP vector get exponent.
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FGETEXP_RND, FGETEXPS_RND,
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// Extract Normalized Mantissas.
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VGETMANT, VGETMANTS,
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VGETMANT, VGETMANT_RND, VGETMANTS, VGETMANTS_RND,
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// FP Scale.
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SCALEF,
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SCALEFS,
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@ -426,11 +426,11 @@ namespace llvm {
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VFIXUPIMM,
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VFIXUPIMMS,
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// Range Restriction Calculation For Packed Pairs of Float32/64 values.
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VRANGE, VRANGES,
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VRANGE, VRANGE_RND, VRANGES, VRANGES_RND,
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// Reduce - Perform Reduction Transformation on scalar\packed FP.
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VREDUCE, VREDUCES,
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VREDUCE, VREDUCE_RND, VREDUCES, VREDUCES_RND,
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// RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
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VRNDSCALE, VRNDSCALES,
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VRNDSCALE, VRNDSCALE_RND, VRNDSCALES, VRNDSCALES_RND,
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// Tests Types Of a FP Values for packed types.
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VFPCLASS,
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// Tests Types Of a FP Values for scalar types.
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@ -7660,12 +7660,12 @@ avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
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"$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 imm:$src3), (i32 FROUND_CURRENT)))>;
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(i32 imm:$src3)))>;
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defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
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"$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
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(_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(_.VT (X86RndScalesRnd (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
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defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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@ -7674,7 +7674,7 @@ avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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"$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (X86RndScales (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
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(i32 imm:$src3), (i32 FROUND_CURRENT)))>;
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(i32 imm:$src3)))>;
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let isCodeGenOnly = 1, hasSideEffects = 0 in {
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def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
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@ -8573,21 +8573,18 @@ multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNo
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(ins _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
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(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2),
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(i32 FROUND_CURRENT))>;
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(i32 imm:$src2))>;
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defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
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(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2),
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(i32 FROUND_CURRENT))>;
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(i32 imm:$src2))>;
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defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.ScalarMemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
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"${src1}"##_.BroadcastStr##", $src2",
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(OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
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(i32 imm:$src2),
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(i32 FROUND_CURRENT))>, EVEX_B;
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(i32 imm:$src2))>, EVEX_B;
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}
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}
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@ -8605,10 +8602,11 @@ multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
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}
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multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
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AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
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AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode,
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SDNode OpNodeRnd, Predicate prd>{
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let Predicates = [prd] in {
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defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
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avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
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avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNodeRnd, _.info512>,
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EVEX_V512;
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}
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let Predicates = [prd, HasVLX] in {
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@ -8631,23 +8629,20 @@ multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(OpNode (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(i32 imm:$src3),
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(i32 FROUND_CURRENT))>;
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(i32 imm:$src3))>;
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defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(OpNode (_.VT _.RC:$src1),
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(_.VT (bitconvert (_.LdFrag addr:$src2))),
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(i32 imm:$src3),
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(i32 FROUND_CURRENT))>;
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(i32 imm:$src3))>;
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defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
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OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr##", $src3",
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(OpNode (_.VT _.RC:$src1),
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(_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
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(i32 imm:$src3),
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(i32 FROUND_CURRENT))>, EVEX_B;
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(i32 imm:$src3))>, EVEX_B;
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}
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}
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@ -8691,7 +8686,6 @@ multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
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//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
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// op(reg_vec2,mem_scalar,imm)
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//all instruction created with FROUND_CURRENT
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multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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let ExeDomain = _.ExeDomain in {
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@ -8700,16 +8694,14 @@ multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(OpNode (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(i32 imm:$src3),
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(i32 FROUND_CURRENT))>;
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(i32 imm:$src3))>;
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defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(OpNode (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector
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(_.ScalarLdFrag addr:$src2))),
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(i32 imm:$src3),
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(i32 FROUND_CURRENT))>;
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(i32 imm:$src3))>;
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}
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}
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@ -8741,10 +8733,11 @@ multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
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}
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multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
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AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
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AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode,
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SDNode OpNodeRnd, Predicate prd>{
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let Predicates = [prd] in {
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defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
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avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
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avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNodeRnd, _.info512>,
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EVEX_V512;
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}
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@ -8782,56 +8775,69 @@ multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
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}
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multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
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X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
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X86VectorVTInfo _, bits<8> opc, SDNode OpNode,
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SDNode OpNodeRnd, Predicate prd>{
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let Predicates = [prd] in {
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defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
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avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
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avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNodeRnd, _>;
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}
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}
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multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
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bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
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bits<8> opcPs, bits<8> opcPd, SDNode OpNode,
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SDNode OpNodeRnd, Predicate prd>{
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defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
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opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
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opcPs, OpNode, OpNodeRnd, prd>, EVEX_CD8<32, CD8VF>;
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defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
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opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
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opcPd, OpNode, OpNodeRnd, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
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}
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defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
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X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
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X86VReduce, X86VReduceRnd, HasDQI>,
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AVX512AIi8Base, EVEX;
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defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
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X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
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X86VRndScale, X86VRndScaleRnd, HasAVX512>,
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AVX512AIi8Base, EVEX;
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defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
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X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
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X86VGetMant, X86VGetMantRnd, HasAVX512>,
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AVX512AIi8Base, EVEX;
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defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
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0x50, X86VRange, HasDQI>,
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0x50, X86VRange,
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X86VRangeRnd, HasDQI>,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
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0x50, X86VRange, HasDQI>,
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0x50, X86VRange,
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X86VRangeRnd, HasDQI>,
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AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
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0x51, X86Ranges, HasDQI>,
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0x51, X86Ranges, X86RangesRnd,
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HasDQI>,
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AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
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defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
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0x51, X86Ranges, HasDQI>,
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0x51, X86Ranges, X86RangesRnd,
|
||||
HasDQI>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
|
||||
0x57, X86Reduces, HasDQI>,
|
||||
0x57, X86Reduces,
|
||||
X86ReducesRnd, HasDQI>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
|
||||
defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
|
||||
0x57, X86Reduces, HasDQI>,
|
||||
0x57, X86Reduces,
|
||||
X86ReducesRnd, HasDQI>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
|
||||
0x27, X86GetMants, HasAVX512>,
|
||||
0x27, X86GetMants,
|
||||
X86GetMantsRnd, HasAVX512>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
|
||||
defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
|
||||
0x27, X86GetMants, HasAVX512>,
|
||||
0x27, X86GetMants,
|
||||
X86GetMantsRnd, HasAVX512>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
let Predicates = [HasAVX512] in {
|
||||
|
||||
@ -298,6 +298,10 @@ def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
|
||||
SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
|
||||
def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
||||
SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
|
||||
def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
|
||||
SDTCisSameAs<0,1>,
|
||||
SDTCisSameAs<0,2>,
|
||||
SDTCisVT<3, i32>]>;
|
||||
def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisVec<0>,
|
||||
SDTCisSameAs<0,1>,
|
||||
SDTCisSameAs<0,2>,
|
||||
@ -310,6 +314,9 @@ def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>,
|
||||
SDTCisSameNumEltsAs<0, 3>,
|
||||
SDTCisVT<4, i32>,
|
||||
SDTCisVT<5, i32>]>;
|
||||
def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisVec<0>,
|
||||
SDTCisSameAs<0,1>,
|
||||
SDTCisVT<2, i32>]>;
|
||||
def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
|
||||
SDTCisSameAs<0,1>,
|
||||
SDTCisVT<2, i32>,
|
||||
@ -419,10 +426,14 @@ def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
|
||||
|
||||
def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>;
|
||||
def X86VFixupimmScalar : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>;
|
||||
def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
|
||||
def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
|
||||
def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
|
||||
def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
|
||||
def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>;
|
||||
def X86VRangeRnd : SDNode<"X86ISD::VRANGE_RND", SDTFPBinOpImmRound>;
|
||||
def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>;
|
||||
def X86VReduceRnd : SDNode<"X86ISD::VREDUCE_RND", SDTFPUnaryOpImmRound>;
|
||||
def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>;
|
||||
def X86VRndScaleRnd: SDNode<"X86ISD::VRNDSCALE_RND", SDTFPUnaryOpImmRound>;
|
||||
def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>;
|
||||
def X86VGetMantRnd : SDNode<"X86ISD::VGETMANT_RND", SDTFPUnaryOpImmRound>;
|
||||
def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
|
||||
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
|
||||
SDTCisFP<1>,
|
||||
@ -517,10 +528,14 @@ def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>;
|
||||
def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>;
|
||||
def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOpRound>;
|
||||
def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOpRound>;
|
||||
def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImmRound>;
|
||||
def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImmRound>;
|
||||
def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImmRound>;
|
||||
def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImmRound>;
|
||||
def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>;
|
||||
def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>;
|
||||
def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>;
|
||||
def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>;
|
||||
def X86RangesRnd : SDNode<"X86ISD::VRANGES_RND", SDTFPBinOpImmRound>;
|
||||
def X86RndScalesRnd : SDNode<"X86ISD::VRNDSCALES_RND", SDTFPBinOpImmRound>;
|
||||
def X86ReducesRnd : SDNode<"X86ISD::VREDUCES_RND", SDTFPBinOpImmRound>;
|
||||
def X86GetMantsRnd : SDNode<"X86ISD::VGETMANTS_RND", SDTFPBinOpImmRound>;
|
||||
|
||||
def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
|
||||
SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
|
||||
|
||||
@ -32,7 +32,7 @@ enum IntrinsicType : uint16_t {
|
||||
FMA_OP_SCALAR_MASK, FMA_OP_SCALAR_MASKZ, FMA_OP_SCALAR_MASK3,
|
||||
IFMA_OP_MASK, IFMA_OP_MASKZ,
|
||||
VPERM_2OP_MASK, VPERM_3OP_MASK, VPERM_3OP_MASKZ, INTR_TYPE_SCALAR_MASK,
|
||||
INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK_RM,
|
||||
INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK,
|
||||
COMPRESS_EXPAND_IN_REG, COMPRESS_TO_MEM,
|
||||
TRUNCATE_TO_MEM_VI8, TRUNCATE_TO_MEM_VI16, TRUNCATE_TO_MEM_VI32,
|
||||
EXPAND_FROM_MEM,
|
||||
@ -730,22 +730,22 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
||||
X86ISD::FGETEXPS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getexp_ss, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FGETEXPS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_pd_128, INTR_TYPE_2OP_MASK_RM,
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_pd_128, INTR_TYPE_2OP_MASK,
|
||||
X86ISD::VGETMANT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_pd_256, INTR_TYPE_2OP_MASK_RM,
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_pd_256, INTR_TYPE_2OP_MASK,
|
||||
X86ISD::VGETMANT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_pd_512, INTR_TYPE_2OP_MASK_RM,
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_pd_512, INTR_TYPE_2OP_MASK,
|
||||
X86ISD::VGETMANT, X86ISD::VGETMANT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ps_128, INTR_TYPE_2OP_MASK,
|
||||
X86ISD::VGETMANT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ps_128, INTR_TYPE_2OP_MASK_RM,
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ps_256, INTR_TYPE_2OP_MASK,
|
||||
X86ISD::VGETMANT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ps_256, INTR_TYPE_2OP_MASK_RM,
|
||||
X86ISD::VGETMANT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ps_512, INTR_TYPE_2OP_MASK_RM,
|
||||
X86ISD::VGETMANT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_sd, INTR_TYPE_3OP_SCALAR_MASK_RM,
|
||||
X86ISD::VGETMANTS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ss, INTR_TYPE_3OP_SCALAR_MASK_RM,
|
||||
X86ISD::VGETMANTS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ps_512, INTR_TYPE_2OP_MASK,
|
||||
X86ISD::VGETMANT, X86ISD::VGETMANT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_sd, INTR_TYPE_3OP_SCALAR_MASK,
|
||||
X86ISD::VGETMANTS, X86ISD::VGETMANTS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ss, INTR_TYPE_3OP_SCALAR_MASK,
|
||||
X86ISD::VGETMANTS, X86ISD::VGETMANTS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FMAX,
|
||||
X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMAX,
|
||||
@ -993,32 +993,32 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
||||
X86ISD::VPTERNLOG, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_pternlog_q_512, TERLOG_OP_MASK,
|
||||
X86ISD::VPTERNLOG, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_pd_128, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_pd_256, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_pd_512, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ps_128, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ps_256, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ps_512, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_sd, INTR_TYPE_SCALAR_MASK_RM, X86ISD::VRANGES, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ss, INTR_TYPE_SCALAR_MASK_RM, X86ISD::VRANGES, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_pd_128, INTR_TYPE_2OP_MASK_RM, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_pd_256, INTR_TYPE_2OP_MASK_RM, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_pd_512, INTR_TYPE_2OP_MASK_RM, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ps_128, INTR_TYPE_2OP_MASK_RM, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ps_256, INTR_TYPE_2OP_MASK_RM, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ps_512, INTR_TYPE_2OP_MASK_RM, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_sd, INTR_TYPE_SCALAR_MASK_RM, X86ISD::VREDUCES, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ss, INTR_TYPE_SCALAR_MASK_RM, X86ISD::VREDUCES, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_pd_128, INTR_TYPE_2OP_MASK_RM, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_pd_256, INTR_TYPE_2OP_MASK_RM, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_pd_512, INTR_TYPE_2OP_MASK_RM, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ps_128, INTR_TYPE_2OP_MASK_RM, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ps_256, INTR_TYPE_2OP_MASK_RM, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ps_512, INTR_TYPE_2OP_MASK_RM, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_sd, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::VRNDSCALES, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ss, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::VRNDSCALES, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_pd_128, INTR_TYPE_3OP_MASK, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_pd_256, INTR_TYPE_3OP_MASK, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_pd_512, INTR_TYPE_3OP_MASK, X86ISD::VRANGE, X86ISD::VRANGE_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ps_128, INTR_TYPE_3OP_MASK, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ps_256, INTR_TYPE_3OP_MASK, X86ISD::VRANGE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ps_512, INTR_TYPE_3OP_MASK, X86ISD::VRANGE, X86ISD::VRANGE_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_sd, INTR_TYPE_SCALAR_MASK, X86ISD::VRANGES, X86ISD::VRANGES_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_range_ss, INTR_TYPE_SCALAR_MASK, X86ISD::VRANGES, X86ISD::VRANGES_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_pd_128, INTR_TYPE_2OP_MASK, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_pd_256, INTR_TYPE_2OP_MASK, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_pd_512, INTR_TYPE_2OP_MASK, X86ISD::VREDUCE, X86ISD::VREDUCE_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ps_128, INTR_TYPE_2OP_MASK, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ps_256, INTR_TYPE_2OP_MASK, X86ISD::VREDUCE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ps_512, INTR_TYPE_2OP_MASK, X86ISD::VREDUCE, X86ISD::VREDUCE_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_sd, INTR_TYPE_SCALAR_MASK, X86ISD::VREDUCES, X86ISD::VREDUCES_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_reduce_ss, INTR_TYPE_SCALAR_MASK, X86ISD::VREDUCES, X86ISD::VREDUCES_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_pd_128, INTR_TYPE_2OP_MASK, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_pd_256, INTR_TYPE_2OP_MASK, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_pd_512, INTR_TYPE_2OP_MASK, X86ISD::VRNDSCALE, X86ISD::VRNDSCALE_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ps_128, INTR_TYPE_2OP_MASK, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ps_256, INTR_TYPE_2OP_MASK, X86ISD::VRNDSCALE, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ps_512, INTR_TYPE_2OP_MASK, X86ISD::VRNDSCALE, X86ISD::VRNDSCALE_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_sd, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::VRNDSCALES, X86ISD::VRNDSCALES_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_rndscale_ss, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::VRNDSCALES, X86ISD::VRNDSCALES_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_scalef_pd_128, INTR_TYPE_2OP_MASK_RM,
|
||||
X86ISD::SCALEF, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_scalef_pd_256, INTR_TYPE_2OP_MASK_RM,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user