mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
LLVM Interpreter: This patch implements vector support for cast operations (zext, sext, uitofp, sitofp, trunc, fpext, fptosi, fptrunc, bitcast) and shift operations (shl, ashr, lshr) for integer and floating point data types.
Added tests. Done by Yuri Veselov (mailto:Yuri.Veselov@intel.com). llvm-svn: 187724
This commit is contained in:
Elena Demikhovsky
parent
39f379d037
commit
c018c20682
@ -1138,15 +1138,41 @@ void Interpreter::visitCallSite(CallSite CS) {
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callFunction((Function*)GVTOP(SRC), ArgVals);
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}
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// auxilary function for shift operations
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static unsigned getShiftAmount(uint64_t orgShiftAmount,
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llvm::APInt valueToShift) {
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unsigned valueWidth = valueToShift.getBitWidth();
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if (orgShiftAmount < (uint64_t)valueWidth)
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return orgShiftAmount;
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// according to the llvm documentation, if orgShiftAmount > valueWidth,
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// the result is undfeined. but we do shift by this rule:
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return (NextPowerOf2(valueWidth-1) - 1) & orgShiftAmount;
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}
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void Interpreter::visitShl(BinaryOperator &I) {
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ExecutionContext &SF = ECStack.back();
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GenericValue Src1 = getOperandValue(I.getOperand(0), SF);
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GenericValue Src2 = getOperandValue(I.getOperand(1), SF);
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GenericValue Dest;
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if (Src2.IntVal.getZExtValue() < Src1.IntVal.getBitWidth())
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Dest.IntVal = Src1.IntVal.shl(Src2.IntVal.getZExtValue());
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else
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Dest.IntVal = Src1.IntVal;
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const Type *Ty = I.getType();
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if (Ty->isVectorTy()) {
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uint32_t src1Size = uint32_t(Src1.AggregateVal.size());
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assert(src1Size == Src2.AggregateVal.size());
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for (unsigned i = 0; i < src1Size; i++) {
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GenericValue Result;
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uint64_t shiftAmount = Src2.AggregateVal[i].IntVal.getZExtValue();
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llvm::APInt valueToShift = Src1.AggregateVal[i].IntVal;
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Result.IntVal = valueToShift.shl(getShiftAmount(shiftAmount, valueToShift));
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Dest.AggregateVal.push_back(Result);
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}
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} else {
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// scalar
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uint64_t shiftAmount = Src2.IntVal.getZExtValue();
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llvm::APInt valueToShift = Src1.IntVal;
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Dest.IntVal = valueToShift.shl(getShiftAmount(shiftAmount, valueToShift));
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}
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SetValue(&I, Dest, SF);
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}
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@ -1156,10 +1182,24 @@ void Interpreter::visitLShr(BinaryOperator &I) {
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GenericValue Src1 = getOperandValue(I.getOperand(0), SF);
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GenericValue Src2 = getOperandValue(I.getOperand(1), SF);
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GenericValue Dest;
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if (Src2.IntVal.getZExtValue() < Src1.IntVal.getBitWidth())
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Dest.IntVal = Src1.IntVal.lshr(Src2.IntVal.getZExtValue());
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else
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Dest.IntVal = Src1.IntVal;
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const Type *Ty = I.getType();
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if (Ty->isVectorTy()) {
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uint32_t src1Size = uint32_t(Src1.AggregateVal.size());
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assert(src1Size == Src2.AggregateVal.size());
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for (unsigned i = 0; i < src1Size; i++) {
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GenericValue Result;
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uint64_t shiftAmount = Src2.AggregateVal[i].IntVal.getZExtValue();
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llvm::APInt valueToShift = Src1.AggregateVal[i].IntVal;
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Result.IntVal = valueToShift.lshr(getShiftAmount(shiftAmount, valueToShift));
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Dest.AggregateVal.push_back(Result);
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}
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} else {
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// scalar
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uint64_t shiftAmount = Src2.IntVal.getZExtValue();
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llvm::APInt valueToShift = Src1.IntVal;
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Dest.IntVal = valueToShift.lshr(getShiftAmount(shiftAmount, valueToShift));
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}
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SetValue(&I, Dest, SF);
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}
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@ -1169,10 +1209,24 @@ void Interpreter::visitAShr(BinaryOperator &I) {
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GenericValue Src1 = getOperandValue(I.getOperand(0), SF);
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GenericValue Src2 = getOperandValue(I.getOperand(1), SF);
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GenericValue Dest;
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if (Src2.IntVal.getZExtValue() < Src1.IntVal.getBitWidth())
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Dest.IntVal = Src1.IntVal.ashr(Src2.IntVal.getZExtValue());
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else
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Dest.IntVal = Src1.IntVal;
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const Type *Ty = I.getType();
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if (Ty->isVectorTy()) {
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size_t src1Size = Src1.AggregateVal.size();
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assert(src1Size == Src2.AggregateVal.size());
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for (unsigned i = 0; i < src1Size; i++) {
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GenericValue Result;
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uint64_t shiftAmount = Src2.AggregateVal[i].IntVal.getZExtValue();
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llvm::APInt valueToShift = Src1.AggregateVal[i].IntVal;
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Result.IntVal = valueToShift.ashr(getShiftAmount(shiftAmount, valueToShift));
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Dest.AggregateVal.push_back(Result);
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}
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} else {
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// scalar
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uint64_t shiftAmount = Src2.IntVal.getZExtValue();
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llvm::APInt valueToShift = Src1.IntVal;
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Dest.IntVal = valueToShift.ashr(getShiftAmount(shiftAmount, valueToShift));
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}
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SetValue(&I, Dest, SF);
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}
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@ -1180,99 +1234,248 @@ void Interpreter::visitAShr(BinaryOperator &I) {
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GenericValue Interpreter::executeTruncInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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Type *SrcTy = SrcVal->getType();
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if (SrcTy->isVectorTy()) {
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Type *DstVecTy = DstTy->getScalarType();
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unsigned DBitWidth = cast<IntegerType>(DstVecTy)->getBitWidth();
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unsigned NumElts = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal
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Dest.AggregateVal.resize(NumElts);
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for (unsigned i = 0; i < NumElts; i++)
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Dest.AggregateVal[i].IntVal = Src.AggregateVal[i].IntVal.trunc(DBitWidth);
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} else {
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IntegerType *DITy = cast<IntegerType>(DstTy);
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unsigned DBitWidth = DITy->getBitWidth();
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Dest.IntVal = Src.IntVal.trunc(DBitWidth);
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}
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return Dest;
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}
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GenericValue Interpreter::executeSExtInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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const Type *SrcTy = SrcVal->getType();
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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IntegerType *DITy = cast<IntegerType>(DstTy);
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if (SrcTy->isVectorTy()) {
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const Type *DstVecTy = DstTy->getScalarType();
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unsigned DBitWidth = cast<IntegerType>(DstVecTy)->getBitWidth();
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal.
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Dest.AggregateVal.resize(size);
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].IntVal = Src.AggregateVal[i].IntVal.sext(DBitWidth);
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} else {
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const IntegerType *DITy = cast<IntegerType>(DstTy);
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unsigned DBitWidth = DITy->getBitWidth();
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Dest.IntVal = Src.IntVal.sext(DBitWidth);
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}
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return Dest;
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}
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GenericValue Interpreter::executeZExtInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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const Type *SrcTy = SrcVal->getType();
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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IntegerType *DITy = cast<IntegerType>(DstTy);
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if (SrcTy->isVectorTy()) {
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const Type *DstVecTy = DstTy->getScalarType();
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unsigned DBitWidth = cast<IntegerType>(DstVecTy)->getBitWidth();
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal.
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Dest.AggregateVal.resize(size);
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].IntVal = Src.AggregateVal[i].IntVal.zext(DBitWidth);
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} else {
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const IntegerType *DITy = cast<IntegerType>(DstTy);
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unsigned DBitWidth = DITy->getBitWidth();
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Dest.IntVal = Src.IntVal.zext(DBitWidth);
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}
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return Dest;
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}
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GenericValue Interpreter::executeFPTruncInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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if (SrcVal->getType()->getTypeID() == Type::VectorTyID) {
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assert(SrcVal->getType()->getScalarType()->isDoubleTy() &&
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DstTy->getScalarType()->isFloatTy() &&
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"Invalid FPTrunc instruction");
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal.
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Dest.AggregateVal.resize(size);
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].FloatVal = (float)Src.AggregateVal[i].DoubleVal;
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} else {
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assert(SrcVal->getType()->isDoubleTy() && DstTy->isFloatTy() &&
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"Invalid FPTrunc instruction");
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Dest.FloatVal = (float)Src.DoubleVal;
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}
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return Dest;
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}
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GenericValue Interpreter::executeFPExtInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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if (SrcVal->getType()->getTypeID() == Type::VectorTyID) {
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assert(SrcVal->getType()->getScalarType()->isFloatTy() &&
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DstTy->getScalarType()->isDoubleTy() && "Invalid FPExt instruction");
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal.
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Dest.AggregateVal.resize(size);
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].DoubleVal = (double)Src.AggregateVal[i].FloatVal;
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} else {
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assert(SrcVal->getType()->isFloatTy() && DstTy->isDoubleTy() &&
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"Invalid FPTrunc instruction");
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"Invalid FPExt instruction");
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Dest.DoubleVal = (double)Src.FloatVal;
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}
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return Dest;
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}
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GenericValue Interpreter::executeFPToUIInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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Type *SrcTy = SrcVal->getType();
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uint32_t DBitWidth = cast<IntegerType>(DstTy)->getBitWidth();
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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if (SrcTy->getTypeID() == Type::VectorTyID) {
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const Type *DstVecTy = DstTy->getScalarType();
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const Type *SrcVecTy = SrcTy->getScalarType();
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uint32_t DBitWidth = cast<IntegerType>(DstVecTy)->getBitWidth();
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal.
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Dest.AggregateVal.resize(size);
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if (SrcVecTy->getTypeID() == Type::FloatTyID) {
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assert(SrcVecTy->isFloatingPointTy() && "Invalid FPToUI instruction");
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].IntVal = APIntOps::RoundFloatToAPInt(
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Src.AggregateVal[i].FloatVal, DBitWidth);
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} else {
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].IntVal = APIntOps::RoundDoubleToAPInt(
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Src.AggregateVal[i].DoubleVal, DBitWidth);
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}
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} else {
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// scalar
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uint32_t DBitWidth = cast<IntegerType>(DstTy)->getBitWidth();
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assert(SrcTy->isFloatingPointTy() && "Invalid FPToUI instruction");
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if (SrcTy->getTypeID() == Type::FloatTyID)
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Dest.IntVal = APIntOps::RoundFloatToAPInt(Src.FloatVal, DBitWidth);
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else
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else {
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Dest.IntVal = APIntOps::RoundDoubleToAPInt(Src.DoubleVal, DBitWidth);
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}
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}
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return Dest;
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}
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GenericValue Interpreter::executeFPToSIInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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Type *SrcTy = SrcVal->getType();
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uint32_t DBitWidth = cast<IntegerType>(DstTy)->getBitWidth();
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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if (SrcTy->getTypeID() == Type::VectorTyID) {
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const Type *DstVecTy = DstTy->getScalarType();
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const Type *SrcVecTy = SrcTy->getScalarType();
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uint32_t DBitWidth = cast<IntegerType>(DstVecTy)->getBitWidth();
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal
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Dest.AggregateVal.resize(size);
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if (SrcVecTy->getTypeID() == Type::FloatTyID) {
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assert(SrcVecTy->isFloatingPointTy() && "Invalid FPToSI instruction");
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].IntVal = APIntOps::RoundFloatToAPInt(
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Src.AggregateVal[i].FloatVal, DBitWidth);
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} else {
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].IntVal = APIntOps::RoundDoubleToAPInt(
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Src.AggregateVal[i].DoubleVal, DBitWidth);
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}
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} else {
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// scalar
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unsigned DBitWidth = cast<IntegerType>(DstTy)->getBitWidth();
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assert(SrcTy->isFloatingPointTy() && "Invalid FPToSI instruction");
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if (SrcTy->getTypeID() == Type::FloatTyID)
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Dest.IntVal = APIntOps::RoundFloatToAPInt(Src.FloatVal, DBitWidth);
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else
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else {
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Dest.IntVal = APIntOps::RoundDoubleToAPInt(Src.DoubleVal, DBitWidth);
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}
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}
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return Dest;
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}
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GenericValue Interpreter::executeUIToFPInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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assert(DstTy->isFloatingPointTy() && "Invalid UIToFP instruction");
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if (SrcVal->getType()->getTypeID() == Type::VectorTyID) {
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const Type *DstVecTy = DstTy->getScalarType();
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal
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Dest.AggregateVal.resize(size);
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if (DstVecTy->getTypeID() == Type::FloatTyID) {
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assert(DstVecTy->isFloatingPointTy() && "Invalid UIToFP instruction");
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].FloatVal =
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APIntOps::RoundAPIntToFloat(Src.AggregateVal[i].IntVal);
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} else {
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].DoubleVal =
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APIntOps::RoundAPIntToDouble(Src.AggregateVal[i].IntVal);
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}
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} else {
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// scalar
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assert(DstTy->isFloatingPointTy() && "Invalid UIToFP instruction");
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if (DstTy->getTypeID() == Type::FloatTyID)
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Dest.FloatVal = APIntOps::RoundAPIntToFloat(Src.IntVal);
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else
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else {
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Dest.DoubleVal = APIntOps::RoundAPIntToDouble(Src.IntVal);
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}
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}
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return Dest;
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}
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GenericValue Interpreter::executeSIToFPInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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if (SrcVal->getType()->getTypeID() == Type::VectorTyID) {
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const Type *DstVecTy = DstTy->getScalarType();
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unsigned size = Src.AggregateVal.size();
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// the sizes of src and dst vectors must be equal
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Dest.AggregateVal.resize(size);
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if (DstVecTy->getTypeID() == Type::FloatTyID) {
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assert(DstVecTy->isFloatingPointTy() && "Invalid SIToFP instruction");
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].FloatVal =
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APIntOps::RoundSignedAPIntToFloat(Src.AggregateVal[i].IntVal);
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} else {
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for (unsigned i = 0; i < size; i++)
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Dest.AggregateVal[i].DoubleVal =
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APIntOps::RoundSignedAPIntToDouble(Src.AggregateVal[i].IntVal);
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}
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} else {
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// scalar
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assert(DstTy->isFloatingPointTy() && "Invalid SIToFP instruction");
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if (DstTy->getTypeID() == Type::FloatTyID)
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Dest.FloatVal = APIntOps::RoundSignedAPIntToFloat(Src.IntVal);
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else
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else {
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Dest.DoubleVal = APIntOps::RoundSignedAPIntToDouble(Src.IntVal);
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return Dest;
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}
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}
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return Dest;
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}
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GenericValue Interpreter::executePtrToIntInst(Value *SrcVal, Type *DstTy,
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@ -1301,32 +1504,166 @@ GenericValue Interpreter::executeIntToPtrInst(Value *SrcVal, Type *DstTy,
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GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy,
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ExecutionContext &SF) {
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// This instruction supports bitwise conversion of vectors to integers and
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// to vectors of other types (as long as they have the same size)
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Type *SrcTy = SrcVal->getType();
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GenericValue Dest, Src = getOperandValue(SrcVal, SF);
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if ((SrcTy->getTypeID() == Type::VectorTyID) ||
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(DstTy->getTypeID() == Type::VectorTyID)) {
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// vector src bitcast to vector dst or vector src bitcast to scalar dst or
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// scalar src bitcast to vector dst
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bool isLittleEndian = TD.isLittleEndian();
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GenericValue TempDst, TempSrc, SrcVec;
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const Type *SrcElemTy;
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const Type *DstElemTy;
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unsigned SrcBitSize;
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unsigned DstBitSize;
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unsigned SrcNum;
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unsigned DstNum;
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if (SrcTy->getTypeID() == Type::VectorTyID) {
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SrcElemTy = SrcTy->getScalarType();
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SrcBitSize = SrcTy->getScalarSizeInBits();
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SrcNum = Src.AggregateVal.size();
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SrcVec = Src;
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} else {
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// if src is scalar value, make it vector <1 x type>
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SrcElemTy = SrcTy;
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SrcBitSize = SrcTy->getPrimitiveSizeInBits();
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SrcNum = 1;
|
||||
SrcVec.AggregateVal.push_back(Src);
|
||||
}
|
||||
|
||||
if (DstTy->getTypeID() == Type::VectorTyID) {
|
||||
DstElemTy = DstTy->getScalarType();
|
||||
DstBitSize = DstTy->getScalarSizeInBits();
|
||||
DstNum = (SrcNum * SrcBitSize) / DstBitSize;
|
||||
} else {
|
||||
DstElemTy = DstTy;
|
||||
DstBitSize = DstTy->getPrimitiveSizeInBits();
|
||||
DstNum = 1;
|
||||
}
|
||||
|
||||
if (SrcNum * SrcBitSize != DstNum * DstBitSize)
|
||||
llvm_unreachable("Invalid BitCast");
|
||||
|
||||
// If src is floating point, cast to integer first.
|
||||
TempSrc.AggregateVal.resize(SrcNum);
|
||||
if (SrcElemTy->isFloatTy()) {
|
||||
for (unsigned i = 0; i < SrcNum; i++)
|
||||
TempSrc.AggregateVal[i].IntVal =
|
||||
APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal);
|
||||
|
||||
} else if (SrcElemTy->isDoubleTy()) {
|
||||
for (unsigned i = 0; i < SrcNum; i++)
|
||||
TempSrc.AggregateVal[i].IntVal =
|
||||
APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal);
|
||||
} else if (SrcElemTy->isIntegerTy()) {
|
||||
for (unsigned i = 0; i < SrcNum; i++)
|
||||
TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal;
|
||||
} else {
|
||||
// Pointers are not allowed as the element type of vector.
|
||||
llvm_unreachable("Invalid Bitcast");
|
||||
}
|
||||
|
||||
// now TempSrc is integer type vector
|
||||
if (DstNum < SrcNum) {
|
||||
// Example: bitcast <4 x i32> <i32 0, i32 1, i32 2, i32 3> to <2 x i64>
|
||||
unsigned Ratio = SrcNum / DstNum;
|
||||
unsigned SrcElt = 0;
|
||||
for (unsigned i = 0; i < DstNum; i++) {
|
||||
GenericValue Elt;
|
||||
Elt.IntVal = 0;
|
||||
Elt.IntVal = Elt.IntVal.zext(DstBitSize);
|
||||
unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1);
|
||||
for (unsigned j = 0; j < Ratio; j++) {
|
||||
APInt Tmp;
|
||||
Tmp = Tmp.zext(SrcBitSize);
|
||||
Tmp = TempSrc.AggregateVal[SrcElt++].IntVal;
|
||||
Tmp = Tmp.zext(DstBitSize);
|
||||
Tmp = Tmp.shl(ShiftAmt);
|
||||
ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
|
||||
Elt.IntVal |= Tmp;
|
||||
}
|
||||
TempDst.AggregateVal.push_back(Elt);
|
||||
}
|
||||
} else {
|
||||
// Example: bitcast <2 x i64> <i64 0, i64 1> to <4 x i32>
|
||||
unsigned Ratio = DstNum / SrcNum;
|
||||
for (unsigned i = 0; i < SrcNum; i++) {
|
||||
unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1);
|
||||
for (unsigned j = 0; j < Ratio; j++) {
|
||||
GenericValue Elt;
|
||||
Elt.IntVal = Elt.IntVal.zext(SrcBitSize);
|
||||
Elt.IntVal = TempSrc.AggregateVal[i].IntVal;
|
||||
Elt.IntVal = Elt.IntVal.lshr(ShiftAmt);
|
||||
// it could be DstBitSize == SrcBitSize, so check it
|
||||
if (DstBitSize < SrcBitSize)
|
||||
Elt.IntVal = Elt.IntVal.trunc(DstBitSize);
|
||||
ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
|
||||
TempDst.AggregateVal.push_back(Elt);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// convert result from integer to specified type
|
||||
if (DstTy->getTypeID() == Type::VectorTyID) {
|
||||
if (DstElemTy->isDoubleTy()) {
|
||||
Dest.AggregateVal.resize(DstNum);
|
||||
for (unsigned i = 0; i < DstNum; i++)
|
||||
Dest.AggregateVal[i].DoubleVal =
|
||||
TempDst.AggregateVal[i].IntVal.bitsToDouble();
|
||||
} else if (DstElemTy->isFloatTy()) {
|
||||
Dest.AggregateVal.resize(DstNum);
|
||||
for (unsigned i = 0; i < DstNum; i++)
|
||||
Dest.AggregateVal[i].FloatVal =
|
||||
TempDst.AggregateVal[i].IntVal.bitsToFloat();
|
||||
} else {
|
||||
Dest = TempDst;
|
||||
}
|
||||
} else {
|
||||
if (DstElemTy->isDoubleTy())
|
||||
Dest.DoubleVal = TempDst.AggregateVal[0].IntVal.bitsToDouble();
|
||||
else if (DstElemTy->isFloatTy()) {
|
||||
Dest.FloatVal = TempDst.AggregateVal[0].IntVal.bitsToFloat();
|
||||
} else {
|
||||
Dest.IntVal = TempDst.AggregateVal[0].IntVal;
|
||||
}
|
||||
}
|
||||
} else { // if ((SrcTy->getTypeID() == Type::VectorTyID) ||
|
||||
// (DstTy->getTypeID() == Type::VectorTyID))
|
||||
|
||||
// scalar src bitcast to scalar dst
|
||||
if (DstTy->isPointerTy()) {
|
||||
assert(SrcTy->isPointerTy() && "Invalid BitCast");
|
||||
Dest.PointerVal = Src.PointerVal;
|
||||
} else if (DstTy->isIntegerTy()) {
|
||||
if (SrcTy->isFloatTy()) {
|
||||
if (SrcTy->isFloatTy())
|
||||
Dest.IntVal = APInt::floatToBits(Src.FloatVal);
|
||||
} else if (SrcTy->isDoubleTy()) {
|
||||
else if (SrcTy->isDoubleTy()) {
|
||||
Dest.IntVal = APInt::doubleToBits(Src.DoubleVal);
|
||||
} else if (SrcTy->isIntegerTy()) {
|
||||
Dest.IntVal = Src.IntVal;
|
||||
} else
|
||||
} else {
|
||||
llvm_unreachable("Invalid BitCast");
|
||||
}
|
||||
} else if (DstTy->isFloatTy()) {
|
||||
if (SrcTy->isIntegerTy())
|
||||
Dest.FloatVal = Src.IntVal.bitsToFloat();
|
||||
else
|
||||
else {
|
||||
Dest.FloatVal = Src.FloatVal;
|
||||
}
|
||||
} else if (DstTy->isDoubleTy()) {
|
||||
if (SrcTy->isIntegerTy())
|
||||
Dest.DoubleVal = Src.IntVal.bitsToDouble();
|
||||
else
|
||||
else {
|
||||
Dest.DoubleVal = Src.DoubleVal;
|
||||
} else
|
||||
}
|
||||
} else {
|
||||
llvm_unreachable("Invalid Bitcast");
|
||||
}
|
||||
}
|
||||
|
||||
return Dest;
|
||||
}
|
||||
|
||||
146
test/ExecutionEngine/test-interp-vec-cast.ll
Normal file
146
test/ExecutionEngine/test-interp-vec-cast.ll
Normal file
@ -0,0 +1,146 @@
|
||||
; RUN: %lli -force-interpreter=true %s > /dev/null
|
||||
|
||||
define i32 @main() {
|
||||
zext <2 x i1> <i1 true,i1 true> to <2 x i8>
|
||||
zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i8>
|
||||
zext <2 x i1> <i1 true,i1 true> to <2 x i16>
|
||||
zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i16>
|
||||
zext <2 x i1> <i1 true,i1 true> to <2 x i32>
|
||||
zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i32>
|
||||
zext <2 x i1> <i1 true,i1 true> to <2 x i64>
|
||||
zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i64>
|
||||
zext <3 x i8> <i8 4, i8 4, i8 4> to <3 x i16>
|
||||
zext <2 x i8> <i8 -4, i8 -4> to <2 x i16>
|
||||
zext <3 x i8> <i8 4, i8 4, i8 4> to <3 x i32>
|
||||
zext <2 x i8> <i8 -4, i8 -4> to <2 x i32>
|
||||
zext <3 x i8> <i8 4, i8 4, i8 4> to <3 x i64>
|
||||
zext <2 x i8> <i8 -4, i8 -4> to <2 x i64>
|
||||
zext <3 x i16> <i16 4, i16 4, i16 4> to <3 x i32>
|
||||
zext <2 x i16> <i16 -4, i16 -4> to <2 x i32>
|
||||
zext <3 x i16> <i16 4, i16 4, i16 4> to <3 x i64>
|
||||
zext <2 x i16> <i16 -4, i16 -4> to <2 x i64>
|
||||
zext <3 x i32> <i32 4, i32 4, i32 4> to <3 x i64>
|
||||
zext <2 x i32> <i32 -4, i32 -4> to <2 x i64>
|
||||
|
||||
|
||||
sext <2 x i1> <i1 true,i1 true> to <2 x i8>
|
||||
sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i8>
|
||||
sext <2 x i1> <i1 true,i1 true> to <2 x i16>
|
||||
sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i16>
|
||||
sext <2 x i1> <i1 true,i1 true> to <2 x i32>
|
||||
sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i32>
|
||||
sext <2 x i1> <i1 true,i1 true> to <2 x i64>
|
||||
sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i64>
|
||||
sext <3 x i8> <i8 -4, i8 0, i8 4> to <3 x i16>
|
||||
sext <2 x i8> <i8 -4, i8 4> to <2 x i16>
|
||||
sext <3 x i8> <i8 -4, i8 0, i8 4> to <3 x i32>
|
||||
sext <2 x i8> <i8 -4, i8 4> to <2 x i32>
|
||||
sext <3 x i8> <i8 -4, i8 0, i8 4> to <3 x i64>
|
||||
sext <2 x i8> <i8 -4, i8 4> to <2 x i64>
|
||||
sext <3 x i16> <i16 -4, i16 0, i16 4> to <3 x i32>
|
||||
sext <2 x i16> <i16 -4, i16 4> to <2 x i32>
|
||||
sext <3 x i16> <i16 -4, i16 0, i16 4> to <3 x i64>
|
||||
sext <2 x i16> <i16 -4, i16 4> to <2 x i64>
|
||||
sext <3 x i32> <i32 -4, i32 0, i32 4> to <3 x i64>
|
||||
sext <2 x i32> <i32 -4, i32 4> to <2 x i64>
|
||||
|
||||
|
||||
uitofp <3 x i1> <i1 true,i1 false,i1 true> to <3 x float>
|
||||
uitofp <2 x i1> <i1 true,i1 true> to <2 x double>
|
||||
uitofp <3 x i8> <i8 -4,i8 0,i8 4> to <3 x float>
|
||||
uitofp <2 x i8> <i8 -4,i8 4> to <2 x double>
|
||||
uitofp <3 x i16> <i16 -4,i16 0,i16 4> to <3 x float>
|
||||
uitofp <2 x i16> <i16 -4,i16 4> to <2 x double>
|
||||
uitofp <3 x i32> <i32 -4,i32 0,i32 4> to <3 x float>
|
||||
uitofp <2 x i32> <i32 -4,i32 4> to <2 x double>
|
||||
uitofp <3 x i64> <i64 -4,i64 0,i64 4> to <3 x float>
|
||||
uitofp <2 x i64> <i64 -4,i64 4> to <2 x double>
|
||||
|
||||
|
||||
sitofp <3 x i1> <i1 true,i1 false,i1 true> to <3 x float>
|
||||
sitofp <2 x i1> <i1 true,i1 true> to <2 x double>
|
||||
sitofp <3 x i8> <i8 -4,i8 0,i8 4> to <3 x float>
|
||||
sitofp <2 x i8> <i8 -4,i8 4> to <2 x double>
|
||||
sitofp <3 x i16> <i16 -4,i16 0,i16 4> to <3 x float>
|
||||
sitofp <2 x i16> <i16 -4,i16 4> to <2 x double>
|
||||
sitofp <3 x i32> <i32 -4,i32 0,i32 4> to <3 x float>
|
||||
sitofp <2 x i32> <i32 -4,i32 4> to <2 x double>
|
||||
sitofp <3 x i64> <i64 -4,i64 0,i64 4> to <3 x float>
|
||||
sitofp <2 x i64> <i64 -4,i64 4> to <2 x double>
|
||||
|
||||
trunc <2 x i16> <i16 -6, i16 6> to <2 x i8>
|
||||
trunc <3 x i16> <i16 -6, i16 6, i16 0> to <3 x i8>
|
||||
trunc <2 x i32> <i32 -6, i32 6> to <2 x i8>
|
||||
trunc <3 x i32> <i32 -6, i32 6, i32 0> to <3 x i8>
|
||||
trunc <2 x i32> <i32 -6, i32 6> to <2 x i16>
|
||||
trunc <3 x i32> <i32 -6, i32 6, i32 0> to <3 x i16>
|
||||
trunc <2 x i64> <i64 -6, i64 6> to <2 x i8>
|
||||
trunc <3 x i64> <i64 -6, i64 6, i64 0> to <3 x i8>
|
||||
trunc <2 x i64> <i64 -6, i64 6> to <2 x i16>
|
||||
trunc <3 x i64> <i64 -6, i64 6, i64 0> to <3 x i16>
|
||||
trunc <2 x i64> <i64 -6, i64 6> to <2 x i32>
|
||||
trunc <3 x i64> <i64 -6, i64 6, i64 0> to <3 x i32>
|
||||
|
||||
|
||||
fpext <2 x float> < float 0.000000e+00, float 1.0> to <2 x double>
|
||||
fpext <3 x float> < float 0.000000e+00, float -1.0, float 1.0> to <3 x double>
|
||||
|
||||
fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i8>
|
||||
fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i8>
|
||||
fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i16>
|
||||
fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i16>
|
||||
fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i32>
|
||||
fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i32>
|
||||
fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i64>
|
||||
fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i64>
|
||||
|
||||
fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i8>
|
||||
fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i8>
|
||||
fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i16>
|
||||
fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i16>
|
||||
fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i32>
|
||||
fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i32>
|
||||
fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i64>
|
||||
fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i64>
|
||||
|
||||
fptrunc <2 x double> < double 0.000000e+00, double 1.0> to <2 x float>
|
||||
fptrunc <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x float>
|
||||
|
||||
bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to <4 x i16>
|
||||
bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to <2 x i32>
|
||||
bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to i64
|
||||
bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to <2 x float>
|
||||
bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to double
|
||||
|
||||
bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to <8 x i8>
|
||||
bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to <2 x i32>
|
||||
bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to i64
|
||||
bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to <2 x float>
|
||||
bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to double
|
||||
|
||||
bitcast <2 x i32> <i32 1, i32 -1> to <8 x i8>
|
||||
bitcast <2 x i32> <i32 1, i32 -1> to <4 x i16>
|
||||
bitcast <2 x i32> <i32 1, i32 -1> to i64
|
||||
bitcast <2 x i32> <i32 1, i32 -1> to <2 x float>
|
||||
bitcast <2 x i32> <i32 1, i32 -1> to double
|
||||
|
||||
bitcast i64 1 to <8 x i8>
|
||||
bitcast i64 1 to <4 x i16>
|
||||
bitcast i64 1 to <2 x i32>
|
||||
bitcast i64 1 to <2 x float>
|
||||
bitcast i64 1 to double
|
||||
|
||||
bitcast <2 x float> <float 1.0, float -1.0> to <8 x i8>
|
||||
bitcast <2 x float> <float 1.0, float -1.0> to <4 x i16>
|
||||
bitcast <2 x float> <float 1.0, float -1.0> to i64
|
||||
bitcast <2 x float> <float 1.0, float -1.0> to <2 x i32>
|
||||
bitcast <2 x float> <float 1.0, float -1.0> to double
|
||||
|
||||
bitcast double 1.0 to <8 x i8>
|
||||
bitcast double 1.0 to <4 x i16>
|
||||
bitcast double 1.0 to <2 x i32>
|
||||
bitcast double 1.0 to <2 x float>
|
||||
bitcast double 1.0 to i64
|
||||
|
||||
ret i32 0
|
||||
}
|
||||
32
test/ExecutionEngine/test-interp-vec-shift.ll
Normal file
32
test/ExecutionEngine/test-interp-vec-shift.ll
Normal file
@ -0,0 +1,32 @@
|
||||
; RUN: %lli -force-interpreter=true %s > /dev/null
|
||||
|
||||
define i32 @main() {
|
||||
%shamt = add <2 x i8> <i8 0, i8 0>, <i8 1, i8 2>
|
||||
%shift.upgrd.1 = zext <2 x i8> %shamt to <2 x i32>
|
||||
%t1.s = shl <2 x i32> <i32 1, i32 2>, %shift.upgrd.1
|
||||
%t2.s = shl <2 x i32> <i32 1, i32 2>, <i32 3, i32 4>
|
||||
%shift.upgrd.2 = zext <2 x i8> %shamt to <2 x i32>
|
||||
%t1 = shl <2 x i32> <i32 1, i32 2>, %shift.upgrd.2
|
||||
%t2 = shl <2 x i32> <i32 1, i32 0>, <i32 5, i32 6>
|
||||
%t2.s.upgrd.3 = shl <2 x i64> <i64 1, i64 2>, <i64 3, i64 4>
|
||||
%t2.upgrd.4 = shl <2 x i64> <i64 1, i64 2>, <i64 6, i64 7>
|
||||
%shift.upgrd.5 = zext <2 x i8> %shamt to <2 x i32>
|
||||
%tr1.s = ashr <2 x i32> <i32 1, i32 2>, %shift.upgrd.5
|
||||
%tr2.s = ashr <2 x i32> <i32 1, i32 2>, <i32 4, i32 5>
|
||||
%shift.upgrd.6 = zext <2 x i8> %shamt to <2 x i32>
|
||||
%tr1 = lshr <2 x i32> <i32 1, i32 2>, %shift.upgrd.6
|
||||
%tr2 = lshr <2 x i32> <i32 1, i32 2>, <i32 5, i32 6>
|
||||
%tr1.l = ashr <2 x i64> <i64 1, i64 2>, <i64 4, i64 5>
|
||||
%shift.upgrd.7 = zext <2 x i8> %shamt to <2 x i64>
|
||||
%tr2.l = ashr <2 x i64> <i64 1, i64 2>, %shift.upgrd.7
|
||||
%tr3.l = shl <2 x i64> <i64 1, i64 2>, <i64 4, i64 5>
|
||||
%shift.upgrd.8 = zext <2 x i8> %shamt to <2 x i64>
|
||||
%tr4.l = shl <2 x i64> <i64 1, i64 2>, %shift.upgrd.8
|
||||
%tr1.u = lshr <2 x i64> <i64 1, i64 2>, <i64 5, i64 6>
|
||||
%shift.upgrd.9 = zext <2 x i8> %shamt to <2 x i64>
|
||||
%tr2.u = lshr <2 x i64> <i64 1, i64 2>, %shift.upgrd.9
|
||||
%tr3.u = shl <2 x i64> <i64 1, i64 2>, <i64 5, i64 6>
|
||||
%shift.upgrd.10 = zext <2 x i8> %shamt to <2 x i64>
|
||||
%tr4.u = shl <2 x i64> <i64 1, i64 2>, %shift.upgrd.10
|
||||
ret i32 0
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user