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Recommit "[X86] Increase the number of instructions searched for isSafeToClobberEFLAGS in a couple places"

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I messed up the bug numbers in the commit message before

Previously this function searched 4 instructions forwards or
backwards to determine if it was ok to clobber eflags.

This is called in 3 places: rematerialization, turning 2 operand
leas into adds or splitting 3 ops leas into an lea and add on some
CPU targets.

This patch increases the search limit to 10 instructions for
rematerialization and 2 operand lea to add. I've left the old
treshold for 3 ops lea spliting as that increases code size.

Fixes PR47024 and PR46315.
This commit is contained in:
Craig Topper 2020-08-08 11:38:50 -07:00
parent 2d70f5fabd
commit c01ba6831e
5 changed files with 25 additions and 6 deletions
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2
lib/Target/X86/X86FixupLEAs.cpp
View File

@ -376,7 +376,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
!TII->isSafeToClobberEFLAGS(MBB, I))
!TII->isSafeToClobberEFLAGS(MBB, I, 10))
return false;
Register DestReg = MI.getOperand(0).getReg();

2
lib/Target/X86/X86InstrInfo.cpp
View File

@ -1127,7 +1127,7 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const {
bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I, 10)) {
// The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
// effects.
int Value;

5
lib/Target/X86/X86InstrInfo.h
View File

@ -442,8 +442,9 @@ public:
/// conservative. If it cannot definitely determine the safety after visiting
/// a few instructions in each direction it assumes it's not safe.
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, 4) ==
MachineBasicBlock::iterator I,
unsigned Neighborhood = 4) const {
return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, Neighborhood) ==
MachineBasicBlock::LQR_Dead;
}

4
test/CodeGen/X86/optimize-max-0.ll
View File

@ -85,7 +85,7 @@ define void @foo(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind {
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: leal 2(%esi), %esi
; CHECK-NEXT: addl $2, %esi
; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl (%esp), %esi ## 4-byte Reload
; CHECK-NEXT: addl %esi, %ecx
@ -513,7 +513,7 @@ define void @bar(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind {
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: leal 2(%edx), %edx
; CHECK-NEXT: addl $2, %edx
; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Reload
; CHECK-NEXT: addl %edx, %eax

18
test/CodeGen/X86/pr47024.ll Normal file
View File

@ -0,0 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
define void @_Z4testv() {
; CHECK-LABEL: _Z4testv:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $21542142465, %rdi # imm = 0x504030201
; CHECK-NEXT: movabsq $723401749922909195, %rdx # imm = 0xA0A0A0F0E0D0C0B
; CHECK-NEXT: movabsq $723401728380766730, %rcx # imm = 0xA0A0A0A0A0A0A0A
; CHECK-NEXT: movabsq $1446803478303675925, %r8 # imm = 0x1414141918171615
; CHECK-NEXT: movabsq $798285110420182026, %r9 # imm = 0xB1414141414140A
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: jmp _Z8process36data_tS_S_ # TAILCALL
tail call void @_Z8process36data_tS_S_(i64 21542142465, i64 0, i64 723401749922909195, i64 723401728380766730, i64 1446803478303675925, i64 798285110420182026)
ret void
}
declare void @_Z8process36data_tS_S_(i64, i64, i64, i64, i64, i64)