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[AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunctionInfo + minor commenting changes

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Differential Revision: http://reviews.llvm.org/D19537

llvm-svn: 267573
This commit is contained in:
Konstantin Zhuravlyov 2016-04-26 17:24:40 +00:00
parent 7177ce0576
commit c01e46c011
6 changed files with 20 additions and 9 deletions
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6
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
View File

@ -478,11 +478,11 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
MaxSGPR += ExtraSGPRs;
// Update necessary Reserved* fields and max VGPRs used if
// "amdgpu-debugger-reserved-trap-regs" was specified.
// "amdgpu-debugger-reserve-trap-regs" attribute was specified.
if (STM.debuggerReserveTrapVGPRs()) {
ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
ProgInfo.ReservedVGPRCount = STM.debuggerReserveTrapVGPRCount();
MaxVGPR += STM.debuggerReserveTrapVGPRCount();
ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount();
MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount();
}
// We found the maximum register index. They start at 0, so add one to get the

3
lib/Target/AMDGPU/AMDGPUAsmPrinter.h
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@ -69,7 +69,10 @@ private:
uint32_t LDSSize;
bool FlatUsed;
// If ReservedVGPRCount is 0 then must be 0. Otherwise, this is the first
// fixed VGPR number reserved.
uint16_t ReservedVGPRFirst;
// The number of consecutive VGPRs reserved.
uint16_t ReservedVGPRCount;
// Bonus information for debugging.

4
lib/Target/AMDGPU/AMDGPUSubtarget.h
View File

@ -314,10 +314,6 @@ public:
return DebuggerReserveTrapVGPRs;
}
unsigned debuggerReserveTrapVGPRCount() const {
return debuggerReserveTrapVGPRs() ? 4 : 0;
}
bool dumpCode() const {
return DumpCode;
}

4
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
View File

@ -49,6 +49,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
PSInputAddr(0),
ReturnsVoid(true),
MaximumWorkGroupSize(0),
DebuggerReserveTrapVGPRCount(0),
LDSWaveSpillSize(0),
PSInputEna(0),
NumUserSGPRs(0),
@ -132,6 +133,9 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
MaximumWorkGroupSize = AMDGPU::getMaximumWorkGroupSize(*F);
else
MaximumWorkGroupSize = ST.getWavefrontSize();
if (ST.debuggerReserveTrapVGPRs())
DebuggerReserveTrapVGPRCount = 4;
}
unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(

7
lib/Target/AMDGPU/SIMachineFunctionInfo.h
View File

@ -62,6 +62,9 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
unsigned MaximumWorkGroupSize;
// Number of reserved VGPRs for trap handler usage.
unsigned DebuggerReserveTrapVGPRCount;
public:
// FIXME: Make private
unsigned LDSWaveSpillSize;
@ -326,6 +329,10 @@ public:
ReturnsVoid = Value;
}
unsigned getDebuggerReserveTrapVGPRCount() const {
return DebuggerReserveTrapVGPRCount;
}
unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
};

5
lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -197,8 +197,9 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// attribute was specified.
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
if (ST.debuggerReserveTrapVGPRs()) {
for (unsigned i = MaxWorkGroupVGPRCount - ST.debuggerReserveTrapVGPRCount();
i < MaxWorkGroupVGPRCount; ++i) {
unsigned ReservedVGPRFirst =
MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount();
for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) {
unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);
}