mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
[RISCV] Use MVT instead of EVT in RISCVISelDAGToDAG.cpp
All this code runs post type legalization so we should have exclusively legal types. The methods on MVT should be more efficient than EVT.
This commit is contained in:
Craig Topper
parent
aa315ff5e6
commit
c021b33a1e
@ -50,7 +50,7 @@ static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
|
||||
return Result;
|
||||
}
|
||||
|
||||
static RISCVVLMUL getLMUL(EVT VT) {
|
||||
static RISCVVLMUL getLMUL(MVT VT) {
|
||||
switch (VT.getSizeInBits().getKnownMinValue() / 8) {
|
||||
default:
|
||||
llvm_unreachable("Invalid LMUL.");
|
||||
@ -71,7 +71,7 @@ static RISCVVLMUL getLMUL(EVT VT) {
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned getSubregIndexByEVT(EVT VT, unsigned Index) {
|
||||
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index) {
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
if (LMUL == RISCVVLMUL::LMUL_F8 || LMUL == RISCVVLMUL::LMUL_F4 ||
|
||||
LMUL == RISCVVLMUL::LMUL_F2 || LMUL == RISCVVLMUL::LMUL_1) {
|
||||
@ -154,7 +154,7 @@ void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, unsigned IntNo,
|
||||
bool IsStrided) {
|
||||
SDLoc DL(Node);
|
||||
unsigned NF = Node->getNumValues() - 1;
|
||||
EVT VT = Node->getValueType(0);
|
||||
MVT VT = Node->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -177,7 +177,7 @@ void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, unsigned IntNo,
|
||||
SDValue SuperReg = SDValue(Load, 0);
|
||||
for (unsigned I = 0; I < NF; ++I)
|
||||
ReplaceUses(SDValue(Node, I),
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByMVT(VT, I), DL,
|
||||
VT, SuperReg));
|
||||
|
||||
ReplaceUses(SDValue(Node, NF), SDValue(Load, 1));
|
||||
@ -188,7 +188,7 @@ void RISCVDAGToDAGISel::selectVLSEGMask(SDNode *Node, unsigned IntNo,
|
||||
bool IsStrided) {
|
||||
SDLoc DL(Node);
|
||||
unsigned NF = Node->getNumValues() - 1;
|
||||
EVT VT = Node->getValueType(0);
|
||||
MVT VT = Node->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -216,7 +216,7 @@ void RISCVDAGToDAGISel::selectVLSEGMask(SDNode *Node, unsigned IntNo,
|
||||
SDValue SuperReg = SDValue(Load, 0);
|
||||
for (unsigned I = 0; I < NF; ++I)
|
||||
ReplaceUses(SDValue(Node, I),
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByMVT(VT, I), DL,
|
||||
VT, SuperReg));
|
||||
|
||||
ReplaceUses(SDValue(Node, NF), SDValue(Load, 1));
|
||||
@ -227,7 +227,7 @@ void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node) {
|
||||
SDLoc DL(Node);
|
||||
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
|
||||
unsigned NF = Node->getNumValues() - 2; // Do not count VL and Chain.
|
||||
EVT VT = Node->getValueType(0);
|
||||
MVT VT = Node->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -248,7 +248,7 @@ void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node) {
|
||||
SDValue SuperReg = SDValue(Load, 0);
|
||||
for (unsigned I = 0; I < NF; ++I)
|
||||
ReplaceUses(SDValue(Node, I),
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByMVT(VT, I), DL,
|
||||
VT, SuperReg));
|
||||
|
||||
ReplaceUses(SDValue(Node, NF), SDValue(ReadVL, 0)); // VL
|
||||
@ -260,7 +260,7 @@ void RISCVDAGToDAGISel::selectVLSEGFFMask(SDNode *Node) {
|
||||
SDLoc DL(Node);
|
||||
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
|
||||
unsigned NF = Node->getNumValues() - 2; // Do not count VL and Chain.
|
||||
EVT VT = Node->getValueType(0);
|
||||
MVT VT = Node->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -285,7 +285,7 @@ void RISCVDAGToDAGISel::selectVLSEGFFMask(SDNode *Node) {
|
||||
SDValue SuperReg = SDValue(Load, 0);
|
||||
for (unsigned I = 0; I < NF; ++I)
|
||||
ReplaceUses(SDValue(Node, I),
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByMVT(VT, I), DL,
|
||||
VT, SuperReg));
|
||||
|
||||
ReplaceUses(SDValue(Node, NF), SDValue(ReadVL, 0)); // VL
|
||||
@ -296,7 +296,7 @@ void RISCVDAGToDAGISel::selectVLSEGFFMask(SDNode *Node) {
|
||||
void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned IntNo) {
|
||||
SDLoc DL(Node);
|
||||
unsigned NF = Node->getNumValues() - 1;
|
||||
EVT VT = Node->getValueType(0);
|
||||
MVT VT = Node->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -308,7 +308,7 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned IntNo) {
|
||||
SEW, Node->getOperand(0) // Chain.
|
||||
};
|
||||
|
||||
EVT IndexVT = Node->getOperand(3)->getValueType(0);
|
||||
MVT IndexVT = Node->getOperand(3)->getSimpleValueType(0);
|
||||
RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
|
||||
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
|
||||
const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
|
||||
@ -319,7 +319,7 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned IntNo) {
|
||||
SDValue SuperReg = SDValue(Load, 0);
|
||||
for (unsigned I = 0; I < NF; ++I)
|
||||
ReplaceUses(SDValue(Node, I),
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByMVT(VT, I), DL,
|
||||
VT, SuperReg));
|
||||
|
||||
ReplaceUses(SDValue(Node, NF), SDValue(Load, 1));
|
||||
@ -329,7 +329,7 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned IntNo) {
|
||||
void RISCVDAGToDAGISel::selectVLXSEGMask(SDNode *Node, unsigned IntNo) {
|
||||
SDLoc DL(Node);
|
||||
unsigned NF = Node->getNumValues() - 1;
|
||||
EVT VT = Node->getValueType(0);
|
||||
MVT VT = Node->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -346,7 +346,7 @@ void RISCVDAGToDAGISel::selectVLXSEGMask(SDNode *Node, unsigned IntNo) {
|
||||
Node->getOperand(0) // Chain.
|
||||
};
|
||||
|
||||
EVT IndexVT = Node->getOperand(NF + 3)->getValueType(0);
|
||||
MVT IndexVT = Node->getOperand(NF + 3)->getSimpleValueType(0);
|
||||
RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
|
||||
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
|
||||
const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
|
||||
@ -357,7 +357,7 @@ void RISCVDAGToDAGISel::selectVLXSEGMask(SDNode *Node, unsigned IntNo) {
|
||||
SDValue SuperReg = SDValue(Load, 0);
|
||||
for (unsigned I = 0; I < NF; ++I)
|
||||
ReplaceUses(SDValue(Node, I),
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
|
||||
CurDAG->getTargetExtractSubreg(getSubregIndexByMVT(VT, I), DL,
|
||||
VT, SuperReg));
|
||||
|
||||
ReplaceUses(SDValue(Node, NF), SDValue(Load, 1));
|
||||
@ -370,7 +370,7 @@ void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, unsigned IntNo,
|
||||
unsigned NF = Node->getNumOperands() - 4;
|
||||
if (IsStrided)
|
||||
NF--;
|
||||
EVT VT = Node->getOperand(2)->getValueType(0);
|
||||
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -402,7 +402,7 @@ void RISCVDAGToDAGISel::selectVSSEGMask(SDNode *Node, unsigned IntNo,
|
||||
unsigned NF = Node->getNumOperands() - 5;
|
||||
if (IsStrided)
|
||||
NF--;
|
||||
EVT VT = Node->getOperand(2)->getValueType(0);
|
||||
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -433,7 +433,7 @@ void RISCVDAGToDAGISel::selectVSSEGMask(SDNode *Node, unsigned IntNo,
|
||||
void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned IntNo) {
|
||||
SDLoc DL(Node);
|
||||
unsigned NF = Node->getNumOperands() - 5;
|
||||
EVT VT = Node->getOperand(2)->getValueType(0);
|
||||
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -449,7 +449,7 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned IntNo) {
|
||||
Node->getOperand(0) // Chain.
|
||||
};
|
||||
|
||||
EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0);
|
||||
MVT IndexVT = Node->getOperand(3 + NF)->getSimpleValueType(0);
|
||||
RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
|
||||
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
|
||||
const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
|
||||
@ -463,7 +463,7 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned IntNo) {
|
||||
void RISCVDAGToDAGISel::selectVSXSEGMask(SDNode *Node, unsigned IntNo) {
|
||||
SDLoc DL(Node);
|
||||
unsigned NF = Node->getNumOperands() - 6;
|
||||
EVT VT = Node->getOperand(2)->getValueType(0);
|
||||
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
|
||||
unsigned ScalarSize = VT.getScalarSizeInBits();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
RISCVVLMUL LMUL = getLMUL(VT);
|
||||
@ -480,7 +480,7 @@ void RISCVDAGToDAGISel::selectVSXSEGMask(SDNode *Node, unsigned IntNo) {
|
||||
Node->getOperand(0) // Chain.
|
||||
};
|
||||
|
||||
EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0);
|
||||
MVT IndexVT = Node->getOperand(3 + NF)->getSimpleValueType(0);
|
||||
RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
|
||||
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
|
||||
const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
|
||||
@ -504,7 +504,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
|
||||
unsigned Opcode = Node->getOpcode();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
SDLoc DL(Node);
|
||||
EVT VT = Node->getValueType(0);
|
||||
MVT VT = Node->getSimpleValueType(0);
|
||||
|
||||
switch (Opcode) {
|
||||
case ISD::ADD: {
|
||||
@ -518,7 +518,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
|
||||
if (!(-4096 <= Imm && Imm <= -2049) && !(2048 <= Imm && Imm <= 4094))
|
||||
break;
|
||||
// Break the imm to imm0+imm1.
|
||||
EVT VT = Node->getValueType(0);
|
||||
const SDValue ImmOp0 = CurDAG->getTargetConstant(Imm - Imm / 2, DL, VT);
|
||||
const SDValue ImmOp1 = CurDAG->getTargetConstant(Imm / 2, DL, VT);
|
||||
auto *NodeAddi0 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT,
|
||||
@ -1003,10 +1002,10 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
|
||||
// any zero-extended immediate.
|
||||
// For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first
|
||||
// sign-extending to (XLenVT -1).
|
||||
auto XLenVT = Subtarget->getXLenVT();
|
||||
MVT XLenVT = Subtarget->getXLenVT();
|
||||
assert(XLenVT == N.getOperand(0).getSimpleValueType() &&
|
||||
"Unexpected splat operand type");
|
||||
auto EltVT = N.getValueType().getVectorElementType();
|
||||
MVT EltVT = N.getSimpleValueType().getVectorElementType();
|
||||
if (EltVT.bitsLT(XLenVT)) {
|
||||
SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits());
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user