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[TableGen] Continue cleaning up .td files

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This pass includes LLVM and MLIR files.

Differential Revision: https://reviews.llvm.org/D93864
This commit is contained in:
Paul C. Anagnostopoulos 2020-12-24 19:02:52 -05:00
parent 52243db396
commit c022e5d275
4 changed files with 23 additions and 23 deletions
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2
include/llvm/IR/IntrinsicsARM.td
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@ -922,7 +922,7 @@ multiclass MVEPredicatedM<list<LLVMType> rets, list<LLVMType> params,
list<IntrinsicProperty> props = [IntrNoMem]> {
def "": Intrinsic<rets, params, props>;
def _predicated: Intrinsic<rets, params # [pred,
!if(!eq(!cast<string>(rets[0]), "llvm_anyvector_ty"),
!if(!eq(rets[0], llvm_anyvector_ty),
LLVMMatchType<0>, rets[0])], props>;
}

36
include/llvm/IR/IntrinsicsNVVM.td
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@ -231,11 +231,11 @@ class NVVM_MMA_OPS<int _ = 0> {
def NVVM_MMA_OPS : NVVM_MMA_OPS;
// Returns [1] if this combination of layout/satf is supported, [] otherwise.
// Returns true if this combination of layout/satf is supported; false otherwise.
// MMA ops must provide all parameters. Loads and stores -- only frags and layout_a.
// The class is used to prevent generation of records for the unsupported variants.
// E.g.
// foreach _ = NVVM_MMA_SUPPORTED<...>.ret in =
// if NVVM_MMA_SUPPORTED<...>.ret then
// def : FOO<>; // The record will only be defined for supported ops.
//
class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b="-", int satf=-1> {
@ -261,20 +261,20 @@ class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b
# !if(!eq(!size(frags), 4),
frags[2].ptx_elt_type # frags[3].ptx_elt_type,
"?");
list<int> ret = !cond(
bit ret = !cond(
// Sub-int MMA only supports fixed A/B layout.
// b1 does not support .satf.
!eq(mma#":"#satf, "b1:row:col:0") : [1],
!eq(mma#":"#satf, "b1:row:col:0") : true,
// mma.m8n8k4 has no .satf modifier.
!and(!eq(frags[0].geom, "m8n8k4"),
!ne(satf, 0)): [],
!ne(satf, 0)): false,
// mma.m8n8k4 has no C=f32 D=f16 variant.
!eq(gcd, "m8n8k4:f32f16"): [],
!eq(mma, "s4:row:col") : [1],
!eq(mma, "u4:row:col") : [1],
!eq(mma, "s4:row:col") : [1],
!eq(mma, "u4:row:col") : [1],
!eq(gcd, "m8n8k4:f32f16"): false,
!eq(mma, "s4:row:col") : true,
!eq(mma, "u4:row:col") : true,
!eq(mma, "s4:row:col") : true,
!eq(mma, "u4:row:col") : true,
// Sub-int load/stores have fixed layout for A and B.
!and(!eq(layout_b, "-"), // It's a Load or Store op
!or(!eq(ld, "b1:a:row"),
@ -288,13 +288,13 @@ class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b
!eq(ld, "u4:a:row"),
!eq(ld, "u4:b:col"),
!eq(ldf, "u4:c"),
!eq(ldf, "u4:d"))) : [1],
!eq(ldf, "u4:d"))) : true,
// All other sub-int ops are not supported.
!eq(t, "b1") : [],
!eq(t, "s4") : [],
!eq(t, "u4") : [],
!eq(t, "b1") : false,
!eq(t, "s4") : false,
!eq(t, "u4") : false,
// All other (non sub-int) are OK.
true: [1]
true: true
);
}
@ -4120,11 +4120,11 @@ class NVVM_WMMA_ST<WMMA_REGS Frag, string Layout, int WithStride>
foreach layout = ["row", "col"] in {
foreach stride = [0, 1] in {
foreach frag = NVVM_MMA_OPS.all_ld_ops in
foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
def WMMA_NAME_LDST<"load", frag, layout, stride>.record
: NVVM_WMMA_LD<frag, layout, stride>;
foreach frag = NVVM_MMA_OPS.all_st_ops in
foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
def WMMA_NAME_LDST<"store", frag, layout, stride>.record
: NVVM_WMMA_ST<frag, layout, stride>;
}
@ -4143,7 +4143,7 @@ foreach layout_a = ["row", "col"] in {
foreach layout_b = ["row", "col"] in {
foreach satf = [0, 1] in {
foreach op = NVVM_MMA_OPS.all_mma_ops in {
foreach _ = NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret in {
if NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret then {
def WMMA_NAME_MMA<layout_a, layout_b, satf,
op[0], op[1], op[2], op[3]>.record
: NVVM_WMMA_MMA<layout_a, layout_b, satf,

2
include/llvm/Option/OptParser.td
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@ -146,7 +146,7 @@ class ValuesCode<code valuecode> { code ValuesCode = valuecode; }
class ImpliedByAnyOf<list<Option> options, code value = "true"> {
code ImpliedCheck = !foldl("false", options, accumulator, option,
!strconcat(accumulator, " || ", !cast<string>(option.KeyPath)));
!strconcat(accumulator, " || ", option.KeyPath));
code ImpliedValue = value;
}

6
lib/Target/NVPTX/NVPTXIntrinsics.td
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@ -7523,10 +7523,10 @@ defset list<WMMA_INSTR> MMA_LDSTs = {
foreach space = [".global", ".shared", ""] in {
foreach addr = [imem, Int32Regs, Int64Regs, MEMri, MEMri64] in {
foreach frag = NVVM_MMA_OPS.all_ld_ops in
foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
def : WMMA_LOAD<WMMA_REGINFO<frag>, layout, space, stride, addr>;
foreach frag = NVVM_MMA_OPS.all_st_ops in
foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
def : WMMA_STORE_D<WMMA_REGINFO<frag>, layout, space, stride, addr>;
} // addr
} // space
@ -7584,7 +7584,7 @@ defset list<WMMA_INSTR> MMAs = {
foreach layout_b = ["row", "col"] in {
foreach satf = [0, 1] in {
foreach op = NVVM_MMA_OPS.all_mma_ops in {
foreach _ = NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret in {
if NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret then {
def : WMMA_MMA<WMMA_REGINFO<op[0]>,
WMMA_REGINFO<op[1]>,
WMMA_REGINFO<op[2]>,