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[TableGen] Continue cleaning up .td files
This pass includes LLVM and MLIR files. Differential Revision: https://reviews.llvm.org/D93864
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@ -922,7 +922,7 @@ multiclass MVEPredicatedM<list<LLVMType> rets, list<LLVMType> params,
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list<IntrinsicProperty> props = [IntrNoMem]> {
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def "": Intrinsic<rets, params, props>;
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def _predicated: Intrinsic<rets, params # [pred,
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!if(!eq(!cast<string>(rets[0]), "llvm_anyvector_ty"),
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!if(!eq(rets[0], llvm_anyvector_ty),
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LLVMMatchType<0>, rets[0])], props>;
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}
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@ -231,11 +231,11 @@ class NVVM_MMA_OPS<int _ = 0> {
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def NVVM_MMA_OPS : NVVM_MMA_OPS;
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// Returns [1] if this combination of layout/satf is supported, [] otherwise.
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// Returns true if this combination of layout/satf is supported; false otherwise.
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// MMA ops must provide all parameters. Loads and stores -- only frags and layout_a.
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// The class is used to prevent generation of records for the unsupported variants.
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// E.g.
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// foreach _ = NVVM_MMA_SUPPORTED<...>.ret in =
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// if NVVM_MMA_SUPPORTED<...>.ret then
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// def : FOO<>; // The record will only be defined for supported ops.
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//
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class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b="-", int satf=-1> {
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@ -261,20 +261,20 @@ class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b
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# !if(!eq(!size(frags), 4),
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frags[2].ptx_elt_type # frags[3].ptx_elt_type,
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"?");
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list<int> ret = !cond(
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bit ret = !cond(
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// Sub-int MMA only supports fixed A/B layout.
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// b1 does not support .satf.
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!eq(mma#":"#satf, "b1:row:col:0") : [1],
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!eq(mma#":"#satf, "b1:row:col:0") : true,
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// mma.m8n8k4 has no .satf modifier.
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!and(!eq(frags[0].geom, "m8n8k4"),
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!ne(satf, 0)): [],
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!ne(satf, 0)): false,
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// mma.m8n8k4 has no C=f32 D=f16 variant.
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!eq(gcd, "m8n8k4:f32f16"): [],
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!eq(mma, "s4:row:col") : [1],
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!eq(mma, "u4:row:col") : [1],
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!eq(mma, "s4:row:col") : [1],
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!eq(mma, "u4:row:col") : [1],
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!eq(gcd, "m8n8k4:f32f16"): false,
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!eq(mma, "s4:row:col") : true,
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!eq(mma, "u4:row:col") : true,
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!eq(mma, "s4:row:col") : true,
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!eq(mma, "u4:row:col") : true,
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// Sub-int load/stores have fixed layout for A and B.
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!and(!eq(layout_b, "-"), // It's a Load or Store op
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!or(!eq(ld, "b1:a:row"),
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@ -288,13 +288,13 @@ class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b
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!eq(ld, "u4:a:row"),
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!eq(ld, "u4:b:col"),
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!eq(ldf, "u4:c"),
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!eq(ldf, "u4:d"))) : [1],
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!eq(ldf, "u4:d"))) : true,
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// All other sub-int ops are not supported.
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!eq(t, "b1") : [],
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!eq(t, "s4") : [],
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!eq(t, "u4") : [],
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!eq(t, "b1") : false,
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!eq(t, "s4") : false,
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!eq(t, "u4") : false,
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// All other (non sub-int) are OK.
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true: [1]
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true: true
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);
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}
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@ -4120,11 +4120,11 @@ class NVVM_WMMA_ST<WMMA_REGS Frag, string Layout, int WithStride>
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foreach layout = ["row", "col"] in {
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foreach stride = [0, 1] in {
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foreach frag = NVVM_MMA_OPS.all_ld_ops in
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foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
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if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
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def WMMA_NAME_LDST<"load", frag, layout, stride>.record
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: NVVM_WMMA_LD<frag, layout, stride>;
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foreach frag = NVVM_MMA_OPS.all_st_ops in
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foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
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if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
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def WMMA_NAME_LDST<"store", frag, layout, stride>.record
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: NVVM_WMMA_ST<frag, layout, stride>;
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}
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@ -4143,7 +4143,7 @@ foreach layout_a = ["row", "col"] in {
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foreach layout_b = ["row", "col"] in {
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foreach satf = [0, 1] in {
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foreach op = NVVM_MMA_OPS.all_mma_ops in {
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foreach _ = NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret in {
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if NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret then {
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def WMMA_NAME_MMA<layout_a, layout_b, satf,
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op[0], op[1], op[2], op[3]>.record
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: NVVM_WMMA_MMA<layout_a, layout_b, satf,
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@ -146,7 +146,7 @@ class ValuesCode<code valuecode> { code ValuesCode = valuecode; }
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class ImpliedByAnyOf<list<Option> options, code value = "true"> {
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code ImpliedCheck = !foldl("false", options, accumulator, option,
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!strconcat(accumulator, " || ", !cast<string>(option.KeyPath)));
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!strconcat(accumulator, " || ", option.KeyPath));
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code ImpliedValue = value;
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}
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@ -7523,10 +7523,10 @@ defset list<WMMA_INSTR> MMA_LDSTs = {
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foreach space = [".global", ".shared", ""] in {
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foreach addr = [imem, Int32Regs, Int64Regs, MEMri, MEMri64] in {
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foreach frag = NVVM_MMA_OPS.all_ld_ops in
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foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
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if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
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def : WMMA_LOAD<WMMA_REGINFO<frag>, layout, space, stride, addr>;
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foreach frag = NVVM_MMA_OPS.all_st_ops in
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foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in
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if NVVM_MMA_SUPPORTED<[frag], layout>.ret then
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def : WMMA_STORE_D<WMMA_REGINFO<frag>, layout, space, stride, addr>;
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} // addr
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} // space
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@ -7584,7 +7584,7 @@ defset list<WMMA_INSTR> MMAs = {
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foreach layout_b = ["row", "col"] in {
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foreach satf = [0, 1] in {
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foreach op = NVVM_MMA_OPS.all_mma_ops in {
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foreach _ = NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret in {
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if NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret then {
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def : WMMA_MMA<WMMA_REGINFO<op[0]>,
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WMMA_REGINFO<op[1]>,
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WMMA_REGINFO<op[2]>,
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