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Demote vectors to arrays. No functionality change.

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llvm-svn: 229861
This commit is contained in:
Benjamin Kramer 2015-02-19 15:26:17 +00:00
parent 6d618f4a18
commit c0850fa665
9 changed files with 77 additions and 151 deletions
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10
lib/CodeGen/SelectionDAG/StatepointLowering.cpp
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@ -607,13 +607,9 @@ void SelectionDAGBuilder::visitStatepoint(const CallInst &CI) {
if (Glue.getNode())
Ops.push_back(Glue);
// Compute return values
SmallVector<EVT, 21> ValueVTs;
ValueVTs.push_back(MVT::Other);
ValueVTs.push_back(MVT::Glue); // provide a glue output since we consume one
// as input. This allows someone else to chain
// off us as needed.
SDVTList NodeTys = DAG.getVTList(ValueVTs);
// Compute return values. Provide a glue output since we consume one as
// input. This allows someone else to chain off us as needed.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
SDNode *StatepointMCNode = DAG.getMachineNode(TargetOpcode::STATEPOINT,
getCurSDLoc(), NodeTys, Ops);

4
lib/Support/YAMLParser.cpp
View File

@ -1528,12 +1528,10 @@ Stream::~Stream() {}
bool Stream::failed() { return scanner->failed(); }
void Stream::printError(Node *N, const Twine &Msg) {
SmallVector<SMRange, 1> Ranges;
Ranges.push_back(N->getSourceRange());
scanner->printError( N->getSourceRange().Start
, SourceMgr::DK_Error
, Msg
, Ranges);
, N->getSourceRange());
}
document_iterator Stream::begin() {

117
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
View File

@ -132,8 +132,8 @@ public:
/// Generic helper for the createDTuple/createQTuple
/// functions. Those should almost always be called instead.
SDValue createTuple(ArrayRef<SDValue> Vecs, unsigned RegClassIDs[],
unsigned SubRegs[]);
SDValue createTuple(ArrayRef<SDValue> Vecs, const unsigned RegClassIDs[],
const unsigned SubRegs[]);
SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
@ -888,26 +888,26 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
}
SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
static unsigned RegClassIDs[] = {
static const unsigned RegClassIDs[] = {
AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
static unsigned SubRegs[] = { AArch64::dsub0, AArch64::dsub1,
AArch64::dsub2, AArch64::dsub3 };
static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1,
AArch64::dsub2, AArch64::dsub3};
return createTuple(Regs, RegClassIDs, SubRegs);
}
SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
static unsigned RegClassIDs[] = {
static const unsigned RegClassIDs[] = {
AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
static unsigned SubRegs[] = { AArch64::qsub0, AArch64::qsub1,
AArch64::qsub2, AArch64::qsub3 };
static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
AArch64::qsub2, AArch64::qsub3};
return createTuple(Regs, RegClassIDs, SubRegs);
}
SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
unsigned RegClassIDs[],
unsigned SubRegs[]) {
const unsigned RegClassIDs[],
const unsigned SubRegs[]) {
// There's no special register-class for a vector-list of 1 element: it's just
// a vector.
if (Regs.size() == 1)
@ -1052,13 +1052,10 @@ SDNode *AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs,
EVT VT = N->getValueType(0);
SDValue Chain = N->getOperand(0);
SmallVector<SDValue, 6> Ops;
Ops.push_back(N->getOperand(2)); // Mem operand;
Ops.push_back(Chain);
SDValue Ops[] = {N->getOperand(2), // Mem operand;
Chain};
std::vector<EVT> ResTys;
ResTys.push_back(MVT::Untyped);
ResTys.push_back(MVT::Other);
EVT ResTys[] = {MVT::Untyped, MVT::Other};
SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
SDValue SuperReg = SDValue(Ld, 0);
@ -1076,15 +1073,12 @@ SDNode *AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
EVT VT = N->getValueType(0);
SDValue Chain = N->getOperand(0);
SmallVector<SDValue, 6> Ops;
Ops.push_back(N->getOperand(1)); // Mem operand
Ops.push_back(N->getOperand(2)); // Incremental
Ops.push_back(Chain);
SDValue Ops[] = {N->getOperand(1), // Mem operand
N->getOperand(2), // Incremental
Chain};
std::vector<EVT> ResTys;
ResTys.push_back(MVT::i64); // Type of the write back register
ResTys.push_back(MVT::Untyped);
ResTys.push_back(MVT::Other);
EVT ResTys[] = {MVT::i64, // Type of the write back register
MVT::Untyped, MVT::Other};
SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
@ -1115,10 +1109,7 @@ SDNode *AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
SmallVector<SDValue, 6> Ops;
Ops.push_back(RegSeq);
Ops.push_back(N->getOperand(NumVecs + 2));
Ops.push_back(N->getOperand(0));
SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
return St;
@ -1128,20 +1119,18 @@ SDNode *AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
unsigned Opc) {
SDLoc dl(N);
EVT VT = N->getOperand(2)->getValueType(0);
SmallVector<EVT, 2> ResTys;
ResTys.push_back(MVT::i64); // Type of the write back register
ResTys.push_back(MVT::Other); // Type for the Chain
EVT ResTys[] = {MVT::i64, // Type of the write back register
MVT::Other}; // Type for the Chain
// Form a REG_SEQUENCE to force register allocation.
bool Is128Bit = VT.getSizeInBits() == 128;
SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
SmallVector<SDValue, 6> Ops;
Ops.push_back(RegSeq);
Ops.push_back(N->getOperand(NumVecs + 1)); // base register
Ops.push_back(N->getOperand(NumVecs + 2)); // Incremental
Ops.push_back(N->getOperand(0)); // Chain
SDValue Ops[] = {RegSeq,
N->getOperand(NumVecs + 1), // base register
N->getOperand(NumVecs + 2), // Incremental
N->getOperand(0)}; // Chain
SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
return St;
@ -1195,18 +1184,13 @@ SDNode *AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
SDValue RegSeq = createQTuple(Regs);
std::vector<EVT> ResTys;
ResTys.push_back(MVT::Untyped);
ResTys.push_back(MVT::Other);
EVT ResTys[] = {MVT::Untyped, MVT::Other};
unsigned LaneNo =
cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
SmallVector<SDValue, 6> Ops;
Ops.push_back(RegSeq);
Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
Ops.push_back(N->getOperand(NumVecs + 3));
Ops.push_back(N->getOperand(0));
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
N->getOperand(NumVecs + 3), N->getOperand(0)};
SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
SDValue SuperReg = SDValue(Ld, 0);
@ -1240,20 +1224,17 @@ SDNode *AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
SDValue RegSeq = createQTuple(Regs);
std::vector<EVT> ResTys;
ResTys.push_back(MVT::i64); // Type of the write back register
ResTys.push_back(MVT::Untyped);
ResTys.push_back(MVT::Other);
EVT ResTys[] = {MVT::i64, // Type of the write back register
MVT::Untyped, MVT::Other};
unsigned LaneNo =
cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
SmallVector<SDValue, 6> Ops;
Ops.push_back(RegSeq);
Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64)); // Lane Number
Ops.push_back(N->getOperand(NumVecs + 2)); // Base register
Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
Ops.push_back(N->getOperand(0));
SDValue Ops[] = {RegSeq,
CurDAG->getTargetConstant(LaneNo, MVT::i64), // Lane Number
N->getOperand(NumVecs + 2), // Base register
N->getOperand(NumVecs + 3), // Incremental
N->getOperand(0)};
SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
// Update uses of the write back register
@ -1301,11 +1282,8 @@ SDNode *AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
unsigned LaneNo =
cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
SmallVector<SDValue, 6> Ops;
Ops.push_back(RegSeq);
Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
Ops.push_back(N->getOperand(NumVecs + 3));
Ops.push_back(N->getOperand(0));
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
N->getOperand(NumVecs + 3), N->getOperand(0)};
SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
// Transfer memoperands.
@ -1331,19 +1309,16 @@ SDNode *AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
SDValue RegSeq = createQTuple(Regs);
SmallVector<EVT, 2> ResTys;
ResTys.push_back(MVT::i64); // Type of the write back register
ResTys.push_back(MVT::Other);
EVT ResTys[] = {MVT::i64, // Type of the write back register
MVT::Other};
unsigned LaneNo =
cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
SmallVector<SDValue, 6> Ops;
Ops.push_back(RegSeq);
Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
Ops.push_back(N->getOperand(NumVecs + 2)); // Base Register
Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
Ops.push_back(N->getOperand(0));
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
N->getOperand(NumVecs + 2), // Base Register
N->getOperand(NumVecs + 3), // Incremental
N->getOperand(0)};
SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
// Transfer memoperands.
@ -2248,11 +2223,7 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
SDValue MemAddr = Node->getOperand(4);
// Place arguments in the right order.
SmallVector<SDValue, 7> Ops;
Ops.push_back(ValLo);
Ops.push_back(ValHi);
Ops.push_back(MemAddr);
Ops.push_back(Chain);
SDValue Ops[] = {ValLo, ValHi, MemAddr, Chain};
SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
// Transfer memoperands.

12
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -979,11 +979,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
} else {
SDValue Zero = DAG.getConstant(0, VT);
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SmallVector<SDValue, 4> Ops;
Ops.push_back(One);
Ops.push_back(Zero);
Ops.push_back(TargetCC);
Ops.push_back(Flag);
SDValue Ops[] = {One, Zero, TargetCC, Flag};
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
}
}
@ -1001,11 +997,7 @@ SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SmallVector<SDValue, 4> Ops;
Ops.push_back(TrueV);
Ops.push_back(FalseV);
Ops.push_back(TargetCC);
Ops.push_back(Flag);
SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
}

40
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -1474,11 +1474,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
LoadRetVTs.push_back(EltVT);
LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue);
SmallVector<SDValue, 4> LoadRetOps;
LoadRetOps.push_back(Chain);
LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
LoadRetOps.push_back(InFlag);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(0, MVT::i32), InFlag};
SDValue retval = DAG.getMemIntrinsicNode(
NVPTXISD::LoadParam, dl,
DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
@ -1504,11 +1501,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
}
LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue);
SmallVector<SDValue, 4> LoadRetOps;
LoadRetOps.push_back(Chain);
LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
LoadRetOps.push_back(InFlag);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(0, MVT::i32), InFlag};
SDValue retval = DAG.getMemIntrinsicNode(
NVPTXISD::LoadParamV2, dl,
DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
@ -1550,11 +1544,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
}
LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue);
SmallVector<SDValue, 4> LoadRetOps;
LoadRetOps.push_back(Chain);
LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
LoadRetOps.push_back(InFlag);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(Ofst, MVT::i32), InFlag};
SDValue retval = DAG.getMemIntrinsicNode(
Opc, dl, DAG.getVTList(LoadRetVTs),
LoadRetOps, EltVT, MachinePointerInfo());
@ -1608,11 +1599,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue);
SmallVector<SDValue, 4> LoadRetOps;
LoadRetOps.push_back(Chain);
LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
LoadRetOps.push_back(DAG.getConstant(Offsets[i], MVT::i32));
LoadRetOps.push_back(InFlag);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(Offsets[i], MVT::i32), InFlag};
SDValue retval = DAG.getMemIntrinsicNode(
NVPTXISD::LoadParam, dl,
DAG.getVTList(LoadRetVTs), LoadRetOps,
@ -4302,11 +4290,8 @@ static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
}
}
SmallVector<SDValue, 8> OtherOps;
// Copy regular operands
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
OtherOps.push_back(N->getOperand(i));
SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
// The select routine does not have access to the LoadSDNode instance, so
// pass along the extension information
@ -4419,8 +4404,7 @@ static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
OtherOps.push_back(Chain); // Chain
// Skip operand 1 (intrinsic ID)
// Others
for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
OtherOps.push_back(N->getOperand(i));
OtherOps.append(N->op_begin() + 2, N->op_end());
MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
@ -4451,9 +4435,7 @@ static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
"Custom handling of non-i8 ldu/ldg?");
// Just copy all operands as-is
SmallVector<SDValue, 4> Ops;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
Ops.push_back(N->getOperand(i));
SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
// Force output to i16
SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);

8
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -1780,12 +1780,8 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
}
}
SmallVector<SDValue, 5> Ops;
Ops.push_back(TrueOp);
Ops.push_back(FalseOp);
Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
Ops.push_back(Glue);
SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, MVT::i32),
DAG.getConstant(C.CCMask, MVT::i32), Glue};
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);

9
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
View File

@ -222,12 +222,9 @@ EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
// Now select between End and null, depending on whether the character
// was found.
SmallVector<SDValue, 5> Ops;
Ops.push_back(End);
Ops.push_back(DAG.getConstant(0, PtrVT));
Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32));
Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32));
Ops.push_back(Glue);
SDValue Ops[] = {End, DAG.getConstant(0, PtrVT),
DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32),
DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32), Glue};
VTs = DAG.getVTList(PtrVT, MVT::Glue);
End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
return std::make_pair(End, Chain);

16
lib/Target/X86/X86ISelLowering.cpp
View File

@ -17115,12 +17115,9 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
// Insert VAARG_64 node into the DAG
// VAARG_64 returns two values: Variable Argument Address, Chain
SmallVector<SDValue, 11> InstOps;
InstOps.push_back(Chain);
InstOps.push_back(SrcPtr);
InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
InstOps.push_back(DAG.getConstant(Align, MVT::i32));
SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
DAG.getConstant(ArgMode, MVT::i8),
DAG.getConstant(Align, MVT::i32)};
SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
VTs, InstOps, MVT::i64,
@ -18039,10 +18036,9 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
false, false, false, 0);
SmallVector<SDValue, 2> Results;
Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
PathThru));
Results.push_back(Chain);
SDValue Results[] = {
DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
Chain};
return DAG.getMergeValues(Results, dl);
}
}

12
lib/Transforms/Utils/SimplifyCFG.cpp
View File

@ -2517,17 +2517,15 @@ static bool SimplifyCondBranchToCondBranch(BranchInst *PBI, BranchInst *BI) {
// The weight to CommonDest should be PredCommon * SuccTotal +
// PredOther * SuccCommon.
// The weight to OtherDest should be PredOther * SuccOther.
SmallVector<uint64_t, 2> NewWeights;
NewWeights.push_back(PredCommon * (SuccCommon + SuccOther) +
PredOther * SuccCommon);
NewWeights.push_back(PredOther * SuccOther);
uint64_t NewWeights[2] = {PredCommon * (SuccCommon + SuccOther) +
PredOther * SuccCommon,
PredOther * SuccOther};
// Halve the weights if any of them cannot fit in an uint32_t
FitWeights(NewWeights);
SmallVector<uint32_t, 2> MDWeights(NewWeights.begin(),NewWeights.end());
PBI->setMetadata(LLVMContext::MD_prof,
MDBuilder(BI->getContext()).
createBranchWeights(MDWeights));
MDBuilder(BI->getContext())
.createBranchWeights(NewWeights[0], NewWeights[1]));
}
// OtherDest may have phi nodes. If so, add an entry from PBI's