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Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info

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for tied register constraints.

llvm-svn: 37601
This commit is contained in:
Chris Lattner 2007-06-15 19:11:01 +00:00
parent f75572a776
commit c08e8abb53
1 changed files with 9 additions and 6 deletions
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15
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -3222,7 +3222,8 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
// Otherwise, if this was a reference to an LLVM register class, create vregs
// for this reference.
std::vector<unsigned> RegClassRegs;
if (PhysReg.second) {
const TargetRegisterClass *RC = PhysReg.second;
if (RC) {
// If this is an early clobber or tied register, our regalloc doesn't know
// how to maintain the constraint. If it isn't, go ahead and create vreg
// and let the regalloc do the right thing.
@ -3272,11 +3273,13 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
// Check to see if this register is allocatable (i.e. don't give out the
// stack pointer).
const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
if (!RC) {
// Make sure we find consecutive registers.
NumAllocated = 0;
continue;
if (RC == 0) {
RC = isAllocatableRegister(Reg, MF, TLI, MRI);
if (!RC) { // Couldn't allocate this register.
// Reset NumAllocated to make sure we return consecutive registers.
NumAllocated = 0;
continue;
}
}
// Okay, this register is good, we can use it.