From c09ecb8c457c9b8ea339e88c2ccebb91c18da51b Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Fri, 29 Sep 2017 10:08:06 +0000 Subject: [PATCH] [mips] Add missing license info, formatting changes. NFCI Add missing license information to MicroMipsInstrFPU.td and fix most of the formatting errors present. Others will be addressed in a follow up commits. llvm-svn: 314505 --- lib/Target/Mips/MicroMipsInstrFPU.td | 77 +++++++++++++++++----------- 1 file changed, 47 insertions(+), 30 deletions(-) diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index f0bbc840487..2fbe930c37b 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -1,3 +1,16 @@ +//==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the microMIPS FPU instruction set. +// +//===----------------------------------------------------------------------===// + let isCodeGenOnly = 1, Predicates = [InMicroMips] in { def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, ADDS_FM_MM<0, 0x30>; @@ -48,8 +61,8 @@ def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6; def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, ROUND_W_FM_MM<0, 0x24>; -def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, - ROUND_W_FM_MM<0, 0xec>; +def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, + II_ROUND>, ROUND_W_FM_MM<0, 0xec>; def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, ROUND_W_FM_MM<1, 0x6c>; @@ -57,8 +70,8 @@ def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, ROUND_W_FM_MM<1, 0x24>; def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, ROUND_W_FM_MM<1, 0x2c>; -def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>, - ROUND_W_FM_MM<1, 0xec>; +def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, + II_ROUND>, ROUND_W_FM_MM<1, 0xec>; def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, ROUND_W_FM_MM<1, 0xac>; @@ -136,15 +149,16 @@ def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, let AdditionalPredicates = [InMicroMips] in { def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, - II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>; + II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>; def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, - FGR32Opnd, II_TRUNC>, ROUND_W_FM_MM<0, 0xac>; + FGR32Opnd, II_TRUNC>, + ROUND_W_FM_MM<0, 0xac>; def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, - ROUND_W_FM_MM<0, 0x6c>; + ROUND_W_FM_MM<0, 0x6c>; def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, - fsqrt>, ROUND_W_FM_MM<0, 0x28>; + fsqrt>, ROUND_W_FM_MM<0, 0x28>; def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; + MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; let DecoderNamespace = "MicroMips" in { @@ -156,12 +170,14 @@ let AdditionalPredicates = [InMicroMips] in { II_RECIP_S>, ROUND_W_FM_MM<0b0, 0b01001000>; def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, - II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>; + II_RECIP_D>, + ROUND_W_FM_MM<0b1, 0b01001000>; def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, ROUND_W_FM_MM<0b0, 0b00001000>; def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, - II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>; + II_RECIP_D>, + ROUND_W_FM_MM<0b1, 0b00001000>; } let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, @@ -177,75 +193,75 @@ let AdditionalPredicates = [InMicroMips] in { } multiclass C_COND_MM fmt, - InstrItinClass itin> { + InstrItinClass itin> { def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.f."#NAME; let isCommutable = 1; } def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.un."#NAME; let isCommutable = 1; } def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.eq."#NAME; let isCommutable = 1; } def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.ueq."#NAME; let isCommutable = 1; } def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.olt."#NAME; } def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.ult."#NAME; } def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.ole."#NAME; } def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.ule."#NAME; } def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.sf."#NAME; let isCommutable = 1; } def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.ngle."#NAME; } def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.seq."#NAME; let isCommutable = 1; } def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.ngl."#NAME; } def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.lt."#NAME; } def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.nge."#NAME; } def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.le."#NAME; } def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, - C_COND_FM_MM { + C_COND_FM_MM { let BaseOpcode = "c.ngt."#NAME; } } @@ -256,7 +272,7 @@ let AdditionalPredicates = [InMicroMips] in { ISA_MIPS1_NOT_32R6_64R6, FGR_32; let DecoderNamespace = "Mips64" in defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, - ISA_MIPS1_NOT_32R6_64R6, FGR_64; + ISA_MIPS1_NOT_32R6_64R6, FGR_64; defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, ISA_MIPS1_NOT_32R6_64R6; @@ -270,7 +286,8 @@ let AdditionalPredicates = [InMicroMips] in { } // To generate NMADD and NMSUB instructions when fneg node is present -let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, InMicroMips, NotMips32r6] in { +let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, + InMicroMips, NotMips32r6] in { defm : NMADD_NMSUB; defm : NMADD_NMSUB; }