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For fastcc on x86, let ECX be used as a return register after EAX and EDX

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llvm-svn: 91410
This commit is contained in:
Kenneth Uildriks 2009-12-15 03:27:52 +00:00
parent 9ebba8d98e
commit c0ab5a6e88
2 changed files with 23 additions and 1 deletions
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9
lib/Target/X86/X86CallingConv.td
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@ -64,11 +64,18 @@ def RetCC_X86_32_C : CallingConv<[
// X86-32 FastCC return-value convention.
def RetCC_X86_32_Fast : CallingConv<[
// The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
// SSE2, otherwise it is the the C calling conventions.
// SSE2.
// This can happen when a float, 2 x float, or 3 x float vector is split by
// target lowering, and is returned in 1-3 sse regs.
CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
// For integers, ECX can be used as an extra return register
CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
// Otherwise, it is the same as the common X86 calling convention.
CCDelegateTo<RetCC_X86Common>
]>;

15
test/CodeGen/X86/fastcc3struct.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llc < %s -march=x86 -o %t
; RUN: grep "movl .48, %ecx" %t
; RUN: grep "movl .24, %edx" %t
; RUN: grep "movl .12, %eax" %t
%0 = type { i32, i32, i32 }
define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
entry:
%0 = insertvalue %0 zeroinitializer, i32 12, 0
%1 = insertvalue %0 %0, i32 24, 1
%2 = insertvalue %0 %1, i32 48, 2
ret %0 %2
}