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[X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r'

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llvm-svn: 320290
This commit is contained in:
Craig Topper 2017-12-10 09:14:38 +00:00
parent 5d2c2efbfb
commit c0b0d99a9c
3 changed files with 22 additions and 22 deletions
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24
lib/Target/X86/X86InstrAVX512.td
View File

@ -4927,7 +4927,7 @@ multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpN
multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNodeRnd,
OpndItins itins, X86VectorVTInfo _> {
let ExeDomain = _.ExeDomain in
defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
defm rrb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
"$rc, $src2, $src1", "$src1, $src2, $rc",
(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc))), itins.rr>,
@ -4937,7 +4937,7 @@ multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDPatternOperat
multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNodeRnd,
OpndItins itins, X86VectorVTInfo _> {
let ExeDomain = _.ExeDomain in
defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
defm rrb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
"{sae}, $src2, $src1", "$src1, $src2, {sae}",
(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC))), itins.rr>,
@ -7487,12 +7487,12 @@ multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src,
OpndItins itins> {
defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest, (outs _dest.RC:$dst),
(ins _src.RC:$src), "vcvtph2ps",
"{sae}, $src", "$src, {sae}",
(X86cvtph2psRnd (_src.VT _src.RC:$src),
(i32 FROUND_NO_EXC)), itins.rr>,
T8PD, EVEX_B, Sched<[itins.Sched]>;
defm rrb : AVX512_maskable<0x13, MRMSrcReg, _dest, (outs _dest.RC:$dst),
(ins _src.RC:$src), "vcvtph2ps",
"{sae}, $src", "$src, {sae}",
(X86cvtph2psRnd (_src.VT _src.RC:$src),
(i32 FROUND_NO_EXC)), itins.rr>,
T8PD, EVEX_B, Sched<[itins.Sched]>;
}
let Predicates = [HasAVX512] in
@ -7602,10 +7602,10 @@ let Predicates = [HasVLX] in {
multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _,
string OpcodeStr, OpndItins itins> {
let hasSideEffects = 0 in
def rb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
!strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
[], itins.rr>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
Sched<[itins.Sched]>;
def rrb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
!strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
[], itins.rr>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
Sched<[itins.Sched]>;
}
let Defs = [EFLAGS], Predicates = [HasAVX512] in {

12
lib/Target/X86/X86InstrInfo.cpp
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@ -10059,9 +10059,9 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const {
case X86::VDIVPDZ256rr:
case X86::VDIVPDZ256rrk:
case X86::VDIVPDZ256rrkz:
case X86::VDIVPDZrb:
case X86::VDIVPDZrbk:
case X86::VDIVPDZrbkz:
case X86::VDIVPDZrrb:
case X86::VDIVPDZrrbk:
case X86::VDIVPDZrrbkz:
case X86::VDIVPDZrm:
case X86::VDIVPDZrmb:
case X86::VDIVPDZrmbk:
@ -10089,9 +10089,9 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const {
case X86::VDIVPSZ256rr:
case X86::VDIVPSZ256rrk:
case X86::VDIVPSZ256rrkz:
case X86::VDIVPSZrb:
case X86::VDIVPSZrbk:
case X86::VDIVPSZrbkz:
case X86::VDIVPSZrrb:
case X86::VDIVPSZrrbk:
case X86::VDIVPSZrrbkz:
case X86::VDIVPSZrm:
case X86::VDIVPSZrmb:
case X86::VDIVPSZrmbk:

8
lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -1560,9 +1560,9 @@ def: InstRW<[SKXWriteResGroup12], (instregex "MOVPQIto64rr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "PMOVMSKBrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "UCOMISDrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "UCOMISSrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VCOMISDZrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VCOMISDZrrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VCOMISDrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VCOMISSZrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VCOMISSZrrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VCOMISSrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VMOVMSKPDYrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VMOVMSKPDrr")>;
@ -1578,9 +1578,9 @@ def: InstRW<[SKXWriteResGroup12], (instregex "VTESTPDYrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VTESTPDrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VTESTPSYrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VTESTPSrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VUCOMISDZrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VUCOMISDZrrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VUCOMISDrr")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VUCOMISSZrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VUCOMISSZrrb")>;
def: InstRW<[SKXWriteResGroup12], (instregex "VUCOMISSrr")>;
def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {