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[PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins
This patch implements the builtins for Vector Load with Zero and Signed Extend Builtins (lxvr_x for b, h, w, d), and adds the appropriate test cases for these builtins. The builtins utilize the vector load instructions itnroduced with ISA 3.1. Differential Revision: https://reviews.llvm.org/D82502#inline-797941
This commit is contained in:
Albion Fung
parent
34d811b345
commit
c16246d9bf
@ -1527,6 +1527,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "PPCISD::STRICT_FCFIDS";
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case PPCISD::STRICT_FCFIDUS:
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return "PPCISD::STRICT_FCFIDUS";
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case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
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}
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return nullptr;
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}
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@ -13639,6 +13640,46 @@ static SDValue combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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// Look for the pattern of a load from a narrow width to i128, feeding
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// into a BUILD_VECTOR of v1i128. Replace this sequence with a PPCISD node
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// (LXVRZX). This node represents a zero extending load that will be matched
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// to the Load VSX Vector Rightmost instructions.
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static SDValue combineBVZEXTLOAD(SDNode *N, SelectionDAG &DAG) {
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SDLoc DL(N);
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// This combine is only eligible for a BUILD_VECTOR of v1i128.
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if (N->getValueType(0) != MVT::v1i128)
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return SDValue();
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SDValue Operand = N->getOperand(0);
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// Proceed with the transformation if the operand to the BUILD_VECTOR
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// is a load instruction.
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if (Operand.getOpcode() != ISD::LOAD)
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return SDValue();
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LoadSDNode *LD = dyn_cast<LoadSDNode>(Operand);
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EVT MemoryType = LD->getMemoryVT();
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// This transformation is only valid if the we are loading either a byte,
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// halfword, word, or doubleword.
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bool ValidLDType = MemoryType == MVT::i8 || MemoryType == MVT::i16 ||
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MemoryType == MVT::i32 || MemoryType == MVT::i64;
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// Ensure that the load from the narrow width is being zero extended to i128.
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if (!ValidLDType ||
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(LD->getExtensionType() != ISD::ZEXTLOAD &&
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LD->getExtensionType() != ISD::EXTLOAD))
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return SDValue();
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SDValue LoadOps[] = {
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LD->getChain(), LD->getBasePtr(),
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DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), DL)};
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return DAG.getMemIntrinsicNode(PPCISD::LXVRZX, DL,
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DAG.getVTList(MVT::v1i128, MVT::Other),
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LoadOps, MemoryType, LD->getMemOperand());
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}
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SDValue PPCTargetLowering::DAGCombineBuildVector(SDNode *N,
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DAGCombinerInfo &DCI) const {
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assert(N->getOpcode() == ISD::BUILD_VECTOR &&
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@ -13676,6 +13717,14 @@ SDValue PPCTargetLowering::DAGCombineBuildVector(SDNode *N,
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return Reduced;
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}
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// On Power10, the Load VSX Vector Rightmost instructions can be utilized
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// if this is a BUILD_VECTOR of v1i128, and if the operand to the BUILD_VECTOR
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// is a load from <valid narrow width> to i128.
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if (Subtarget.isISA3_1()) {
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SDValue BVOfZLoad = combineBVZEXTLOAD(N, DAG);
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if (BVOfZLoad)
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return BVOfZLoad;
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}
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if (N->getValueType(0) != MVT::v2f64)
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return SDValue();
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@ -494,6 +494,12 @@ namespace llvm {
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/// an xxswapd.
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LXVD2X,
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/// LXVRZX - Load VSX Vector Rightmost and Zero Extend
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/// This node represents v1i128 BUILD_VECTOR of a zero extending load
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/// instruction from <byte, halfword, word, or doubleword> to i128.
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/// Allows utilization of the Load VSX Vector Rightmost Instructions.
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LXVRZX,
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/// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
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/// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
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/// the vector type to load vector in big-endian element order.
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@ -18,6 +18,15 @@ def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>;
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// address computations).
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class isPCRel { bit PCRel = 1; }
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// PowerPC specific type constraints.
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def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [
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SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
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]>;
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// PPC Specific DAG Nodes.
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def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
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[SDNPHasChain, SDNPMayLoad]>;
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// Top-level class for prefixed instructions.
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class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin> : Instruction {
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@ -1326,6 +1335,15 @@ let Predicates = [IsISA3_1] in {
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(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
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def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
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(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
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def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 8)),
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(v1i128 (COPY_TO_REGCLASS (LXVRBX xoaddr:$src), VRRC))>;
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def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 16)),
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(v1i128 (COPY_TO_REGCLASS (LXVRHX xoaddr:$src), VRRC))>;
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def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 32)),
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(v1i128 (COPY_TO_REGCLASS (LXVRWX xoaddr:$src), VRRC))>;
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def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 64)),
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(v1i128 (COPY_TO_REGCLASS (LXVRDX xoaddr:$src), VRRC))>;
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}
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let AddedComplexity = 400, Predicates = [IsISA3_1] in {
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@ -239,3 +239,181 @@ entry:
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store i64 %conv, i64* %add.ptr, align 8
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ret void
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}
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define dso_local <1 x i128> @vec_xl_zext(i64 %__offset, i8* nocapture readonly %__pointer) {
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; CHECK-LABEL: vec_xl_zext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvrbx v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_zext:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: lxvrbx vs0, r4, r3
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; CHECK-O0-NEXT: xxlor v2, vs0, vs0
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i8, i8* %__pointer, i64 %__offset
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%0 = load i8, i8* %add.ptr, align 1
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%conv = zext i8 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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define dso_local <1 x i128> @vec_xl_zext_short(i64 %__offset, i16* nocapture readonly %__pointer) {
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; CHECK-LABEL: vec_xl_zext_short:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sldi r3, r3, 1
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; CHECK-NEXT: lxvrhx v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_zext_short:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: sldi r3, r3, 1
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; CHECK-O0-NEXT: lxvrhx vs0, r4, r3
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; CHECK-O0-NEXT: xxlor v2, vs0, vs0
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i16, i16* %__pointer, i64 %__offset
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%0 = load i16, i16* %add.ptr, align 2
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%conv = zext i16 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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define dso_local <1 x i128> @vec_xl_zext_word(i64 %__offset, i32* nocapture readonly %__pointer) {
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; CHECK-LABEL: vec_xl_zext_word:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sldi r3, r3, 2
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; CHECK-NEXT: lxvrwx v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_zext_word:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: sldi r3, r3, 2
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; CHECK-O0-NEXT: lxvrwx vs0, r4, r3
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; CHECK-O0-NEXT: xxlor v2, vs0, vs0
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i32, i32* %__pointer, i64 %__offset
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%0 = load i32, i32* %add.ptr, align 4
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%conv = zext i32 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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define dso_local <1 x i128> @vec_xl_zext_dw(i64 %__offset, i64* nocapture readonly %__pointer) {
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; CHECK-LABEL: vec_xl_zext_dw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sldi r3, r3, 3
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; CHECK-NEXT: lxvrdx v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_zext_dw:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: sldi r3, r3, 3
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; CHECK-O0-NEXT: lxvrdx vs0, r4, r3
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; CHECK-O0-NEXT: xxlor v2, vs0, vs0
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i64, i64* %__pointer, i64 %__offset
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%0 = load i64, i64* %add.ptr, align 8
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%conv = zext i64 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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define dso_local <1 x i128> @vec_xl_sext_b(i64 %offset, i8* %p) {
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; CHECK-LABEL: vec_xl_sext_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lbzx r3, r4, r3
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; CHECK-NEXT: extsb r3, r3
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; CHECK-NEXT: sradi r4, r3, 63
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; CHECK-NEXT: mtvsrdd v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_sext_b:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: lbzx r3, r4, r3
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; CHECK-O0-NEXT: extsb r3, r3
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; CHECK-O0-NEXT: sradi r4, r3, 63
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; CHECK-O0-NEXT: mtvsrdd v2, r4, r3
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i8, i8* %p, i64 %offset
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%0 = load i8, i8* %add.ptr, align 1
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%conv = sext i8 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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define dso_local <1 x i128> @vec_xl_sext_h(i64 %offset, i16* %p) {
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; CHECK-LABEL: vec_xl_sext_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sldi r3, r3, 1
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; CHECK-NEXT: lhax r3, r4, r3
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; CHECK-NEXT: sradi r4, r3, 63
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; CHECK-NEXT: mtvsrdd v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_sext_h:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: sldi r3, r3, 1
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; CHECK-O0-NEXT: lhax r3, r4, r3
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; CHECK-O0-NEXT: sradi r4, r3, 63
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; CHECK-O0-NEXT: mtvsrdd v2, r4, r3
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i16, i16* %p, i64 %offset
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%0 = load i16, i16* %add.ptr, align 2
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%conv = sext i16 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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define dso_local <1 x i128> @vec_xl_sext_w(i64 %offset, i32* %p) {
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; CHECK-LABEL: vec_xl_sext_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sldi r3, r3, 2
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; CHECK-NEXT: lwax r3, r4, r3
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; CHECK-NEXT: sradi r4, r3, 63
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; CHECK-NEXT: mtvsrdd v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_sext_w:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: sldi r3, r3, 2
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; CHECK-O0-NEXT: lwax r3, r4, r3
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; CHECK-O0-NEXT: sradi r4, r3, 63
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; CHECK-O0-NEXT: mtvsrdd v2, r4, r3
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 %offset
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%0 = load i32, i32* %add.ptr, align 4
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%conv = sext i32 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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define dso_local <1 x i128> @vec_xl_sext_d(i64 %offset, i64* %p) {
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; CHECK-LABEL: vec_xl_sext_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sldi r3, r3, 3
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; CHECK-NEXT: ldx r3, r4, r3
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; CHECK-NEXT: sradi r4, r3, 63
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; CHECK-NEXT: mtvsrdd v2, r4, r3
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; CHECK-NEXT: blr
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;
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; CHECK-O0-LABEL: vec_xl_sext_d:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: sldi r3, r3, 3
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; CHECK-O0-NEXT: ldx r3, r4, r3
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; CHECK-O0-NEXT: sradi r4, r3, 63
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; CHECK-O0-NEXT: mtvsrdd v2, r4, r3
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; CHECK-O0-NEXT: blr
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entry:
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%add.ptr = getelementptr inbounds i64, i64* %p, i64 %offset
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%0 = load i64, i64* %add.ptr, align 8
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%conv = sext i64 %0 to i128
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%splat.splatinsert = insertelement <1 x i128> undef, i128 %conv, i32 0
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ret <1 x i128> %splat.splatinsert
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}
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