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Select optimization
llvm-svn: 21051
This commit is contained in:
Andrew Lenharth
parent
bd19c1d25f
commit
c16ede8779
@ -335,6 +335,8 @@ public:
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void SelectBranchCC(SDOperand N);
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void MoveFP2Int(unsigned src, unsigned dst, bool isDouble);
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void MoveInt2FP(unsigned src, unsigned dst, bool isDouble);
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//returns whether the sense of the comparison was inverted
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bool SelectFPSetCC(SDOperand N, unsigned dst);
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};
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}
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@ -418,6 +420,64 @@ void ISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
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}
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}
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bool ISel::SelectFPSetCC(SDOperand N, unsigned dst)
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{
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SDNode *Node = N.Val;
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unsigned Opc, Tmp1, Tmp2, Tmp3;
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SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node);
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//assert(SetCC->getOperand(0).getValueType() != MVT::f32 && "SetCC f32 should have been promoted");
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bool rev = false;
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bool inv = false;
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switch (SetCC->getCondition()) {
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default: Node->dump(); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
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case ISD::SETLT: Opc = Alpha::CMPTLT; break;
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case ISD::SETLE: Opc = Alpha::CMPTLE; break;
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case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
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case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
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case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
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}
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//FIXME: check for constant 0.0
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ConstantFPSDNode *CN;
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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Tmp1 = Alpha::F31;
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else
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Tmp1 = SelectExpr(N.getOperand(0));
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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Tmp2 = Alpha::F31;
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else
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Tmp2 = SelectExpr(N.getOperand(1));
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//Can only compare doubles, and dag won't promote for me
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if (SetCC->getOperand(0).getValueType() == MVT::f32)
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{
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//assert(0 && "Setcc On float?\n");
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std::cerr << "Setcc on float!\n";
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Tmp3 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1);
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Tmp1 = Tmp3;
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}
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if (SetCC->getOperand(1).getValueType() == MVT::f32)
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{
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//assert (0 && "Setcc On float?\n");
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std::cerr << "Setcc on float!\n";
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Tmp3 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2);
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Tmp2 = Tmp3;
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}
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if (rev) std::swap(Tmp1, Tmp2);
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//do the comparison
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BuildMI(BB, Opc, 2, dst).addReg(Tmp1).addReg(Tmp2);
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return inv;
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}
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//Check to see if the load is a constant offset from a base register
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void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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{
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@ -1318,62 +1378,15 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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}
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} else {
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//assert(SetCC->getOperand(0).getValueType() != MVT::f32 && "SetCC f32 should have been promoted");
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bool rev = false;
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bool inv = false;
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switch (SetCC->getCondition()) {
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default: Node->dump(); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
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case ISD::SETLT: Opc = Alpha::CMPTLT; break;
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case ISD::SETLE: Opc = Alpha::CMPTLE; break;
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case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
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case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
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case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
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}
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//FIXME: check for constant 0.0
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ConstantFPSDNode *CN;
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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Tmp1 = Alpha::F31;
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else
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Tmp1 = SelectExpr(N.getOperand(0));
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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Tmp2 = Alpha::F31;
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else
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Tmp2 = SelectExpr(N.getOperand(1));
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//Can only compare doubles, and dag won't promote for me
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if (SetCC->getOperand(0).getValueType() == MVT::f32)
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{
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//assert(0 && "Setcc On float?\n");
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std::cerr << "Setcc on float!\n";
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Tmp3 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1);
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Tmp1 = Tmp3;
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}
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if (SetCC->getOperand(1).getValueType() == MVT::f32)
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{
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//assert (0 && "Setcc On float?\n");
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std::cerr << "Setcc on float!\n";
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Tmp3 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2);
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Tmp2 = Tmp3;
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}
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if (rev) std::swap(Tmp1, Tmp2);
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Tmp3 = MakeReg(MVT::f64);
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//do the comparison
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BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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Tmp1 = MakeReg(MVT::f64);
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bool inv = SelectFPSetCC(N, Tmp1);
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//now arrange for Result (int) to have a 1 or 0
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unsigned Tmp4 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::ADDQi, 2, Tmp4).addReg(Alpha::R31).addImm(1);
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Tmp2 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::ADDQi, 2, Tmp2).addReg(Alpha::R31).addImm(1);
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Opc = inv?Alpha::CMOVNEi_FP:Alpha::CMOVEQi_FP;
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BuildMI(BB, Opc, 3, Result).addReg(Tmp4).addImm(0).addReg(Tmp3);
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BuildMI(BB, Opc, 3, Result).addReg(Tmp2).addImm(0).addReg(Tmp1);
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}
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}
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return Result;
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@ -1554,16 +1567,88 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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}
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// // case ISD::FP_TO_UINT:
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case ISD::SELECT:
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{
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//FIXME: look at parent to decide if intCC can be folded, or if setCC(FP) and can save stack use
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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//Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
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Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
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// Get the condition into the zero flag.
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//BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
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SDOperand CC = N.getOperand(0);
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
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if (CC.getOpcode() == ISD::SETCC &&
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!MVT::isInteger(SetCC->getOperand(0).getValueType()))
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{ //FP Setcc -> Int Select
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Tmp1 = MakeReg(MVT::f64);
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bool inv = SelectFPSetCC(CC, Tmp1);
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BuildMI(BB, inv?Alpha::CMOVNE_FP:Alpha::CMOVEQ_FP, 2, Result)
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.addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
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return Result;
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}
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if (CC.getOpcode() == ISD::SETCC) {
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//Int SetCC -> Select
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//Dropping the CC is only useful if we are comparing to 0
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if(SetCC->getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0)
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{
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bool useI = (SetCC->getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() <= 255);
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switch (SetCC->getCondition()) {
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default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ: Opc = useI?Alpha::CMOVEQi:Alpha::CMOVEQ; break;
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case ISD::SETLT: Opc = useI?Alpha::CMOVGTi:Alpha::CMOVGT; break;
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case ISD::SETLE: Opc = useI?Alpha::CMOVGEi:Alpha::CMOVGE; break;
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case ISD::SETGT: Opc = useI?Alpha::CMOVLTi:Alpha::CMOVLT; break;
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case ISD::SETGE: Opc = useI?Alpha::CMOVLEi:Alpha::CMOVLE; break;
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case ISD::SETULT: Opc = useI?Alpha::CMOVNEi:Alpha::CMOVNE; break;
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case ISD::SETUGT: assert(0 && "0 > (unsigned) x is never true"); break;
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case ISD::SETULE: assert(0 && "0 <= (unsigned) x is always true"); break;
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case ISD::SETUGE: Opc = useI?Alpha::CMOVEQi:Alpha::CMOVEQ; break; //Technically you could have this CC
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case ISD::SETNE: Opc = useI?Alpha::CMOVNEi:Alpha::CMOVNE; break;
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}
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if (useI)
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BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(Tmp3)
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.addImm(cast<ConstantSDNode>(SetCC->getOperand(1))->getValue());
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else
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BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(Tmp3)
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.addReg(SelectExpr(SetCC->getOperand(1)));
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return Result;
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}
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if(SetCC->getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0)
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{
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bool useI = (SetCC->getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() <= 255);
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switch (SetCC->getCondition()) {
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default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ: Opc = useI?Alpha::CMOVEQi:Alpha::CMOVEQ; break;
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case ISD::SETLT: Opc = useI?Alpha::CMOVLTi:Alpha::CMOVLT; break;
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case ISD::SETLE: Opc = useI?Alpha::CMOVLEi:Alpha::CMOVLE; break;
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case ISD::SETGT: Opc = useI?Alpha::CMOVGTi:Alpha::CMOVGT; break;
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case ISD::SETGE: Opc = useI?Alpha::CMOVGEi:Alpha::CMOVGE; break;
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case ISD::SETULT: assert(0 && "x (unsigned) < 0 is never true"); break;
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case ISD::SETUGT: Opc = useI?Alpha::CMOVNEi:Alpha::CMOVNE; break;
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case ISD::SETULE: Opc = useI?Alpha::CMOVEQi:Alpha::CMOVEQ; break; //Technically you could have this CC
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case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
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case ISD::SETNE: Opc = useI?Alpha::CMOVNEi:Alpha::CMOVNE; break;
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}
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if (useI)
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BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(Tmp3)
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.addImm(cast<ConstantSDNode>(SetCC->getOperand(0))->getValue());
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else
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BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(Tmp3)
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.addReg(SelectExpr(SetCC->getOperand(0)));
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return Result;
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}
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//Otherwise, fall though
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}
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Tmp1 = SelectExpr(N.getOperand(0)); //Cond
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BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
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return Result;
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}
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@ -55,6 +55,7 @@ let isCall = 1,
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let isReturn = 1, isTerminator = 1 in
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def RETURN : PseudoInstAlpha<(ops ), "ret $$31,($$26),1">; //Return from subroutine
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//These are evil as they get expanded into multiple instructions to take care of reallocation
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let Uses = [R29], Defs = [R28] in {
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def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address
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def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
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@ -80,6 +81,7 @@ let Uses = [R29], Defs = [R28] in {
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//RESULTS of these go to R27
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//These are also evil as the assembler expands them into calls
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let Uses = [R29],
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Defs = [R28, R23, R24, R25, R27] in
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{
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