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[RISCV] Implement adding a displacement to a BlockAddress
Recent change rL357393 uses MachineInstrBuilder::addDisp to add a based on a BlockAddress but this case was not implemented. This patch adds the missing case and a test for RISC-V that exercises the new case. Differential Revision: https://reviews.llvm.org/D60136 llvm-svn: 357752
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@ -287,6 +287,9 @@ public:
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case MachineOperand::MO_GlobalAddress:
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return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
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TargetFlags);
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case MachineOperand::MO_BlockAddress:
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return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
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TargetFlags);
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}
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}
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@ -52,14 +52,88 @@ block:
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unreachable
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}
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; Check lowering of blockaddress that forces a displacement to be added
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define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
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; RV32I-SMALL-LABEL: lower_blockaddress_displ:
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; RV32I-SMALL: # %bb.0: # %entry
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; RV32I-SMALL-NEXT: addi sp, sp, -16
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; RV32I-SMALL-NEXT: sw ra, 12(sp)
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; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0)
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; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)
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; RV32I-SMALL-NEXT: sw a1, 8(sp)
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; RV32I-SMALL-NEXT: addi a1, zero, 101
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; RV32I-SMALL-NEXT: blt a0, a1, .LBB2_3
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; RV32I-SMALL-NEXT: # %bb.1: # %if.then
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; RV32I-SMALL-NEXT: lw a0, 8(sp)
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; RV32I-SMALL-NEXT: jr a0
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; RV32I-SMALL-NEXT: .Ltmp0: # Block address taken
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; RV32I-SMALL-NEXT: .LBB2_2: # %return
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; RV32I-SMALL-NEXT: addi a0, zero, 4
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; RV32I-SMALL-NEXT: j .LBB2_4
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; RV32I-SMALL-NEXT: .LBB2_3: # %return.clone
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; RV32I-SMALL-NEXT: addi a0, zero, 3
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; RV32I-SMALL-NEXT: .LBB2_4: # %.split
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; RV32I-SMALL-NEXT: lw ra, 12(sp)
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; RV32I-SMALL-NEXT: addi sp, sp, 16
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; RV32I-SMALL-NEXT: ret
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;
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; RV32I-MEDIUM-LABEL: lower_blockaddress_displ:
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; RV32I-MEDIUM: # %bb.0: # %entry
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; RV32I-MEDIUM-NEXT: addi sp, sp, -16
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; RV32I-MEDIUM-NEXT: sw ra, 12(sp)
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; RV32I-MEDIUM-NEXT: .LBB2_5: # %entry
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; RV32I-MEDIUM-NEXT: # Label of block must be emitted
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; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)
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; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_5)
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; RV32I-MEDIUM-NEXT: sw a1, 8(sp)
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; RV32I-MEDIUM-NEXT: addi a1, zero, 101
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; RV32I-MEDIUM-NEXT: blt a0, a1, .LBB2_3
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; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then
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; RV32I-MEDIUM-NEXT: lw a0, 8(sp)
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; RV32I-MEDIUM-NEXT: jr a0
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; RV32I-MEDIUM-NEXT: .Ltmp0: # Block address taken
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; RV32I-MEDIUM-NEXT: .LBB2_2: # %return
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; RV32I-MEDIUM-NEXT: addi a0, zero, 4
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; RV32I-MEDIUM-NEXT: j .LBB2_4
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; RV32I-MEDIUM-NEXT: .LBB2_3: # %return.clone
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; RV32I-MEDIUM-NEXT: addi a0, zero, 3
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; RV32I-MEDIUM-NEXT: .LBB2_4: # %.split
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; RV32I-MEDIUM-NEXT: lw ra, 12(sp)
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; RV32I-MEDIUM-NEXT: addi sp, sp, 16
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; RV32I-MEDIUM-NEXT: ret
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entry:
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%x = alloca i8*, align 8
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store i8* blockaddress(@lower_blockaddress_displ, %test_block), i8** %x, align 8
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%cmp = icmp sgt i32 %w, 100
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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%addr = load i8*, i8** %x, align 8
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br label %indirectgoto
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if.end:
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br label %return
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test_block:
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br label %return
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return:
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%retval = phi i32 [ 3, %if.end ], [ 4, %test_block ]
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ret i32 %retval
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indirectgoto:
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indirectbr i8* %addr, [ label %test_block ]
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}
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; Check lowering of constantpools
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define float @lower_constantpool(float %a) nounwind {
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; RV32I-SMALL-LABEL: lower_constantpool:
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; RV32I-SMALL: # %bb.0:
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; RV32I-SMALL-NEXT: fmv.w.x ft0, a0
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; RV32I-SMALL-NEXT: lui a0, %hi(.LCPI2_0)
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; RV32I-SMALL-NEXT: addi a0, a0, %lo(.LCPI2_0)
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; RV32I-SMALL-NEXT: lui a0, %hi(.LCPI3_0)
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; RV32I-SMALL-NEXT: addi a0, a0, %lo(.LCPI3_0)
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; RV32I-SMALL-NEXT: flw ft1, 0(a0)
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; RV32I-SMALL-NEXT: fadd.s ft0, ft0, ft1
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; RV32I-SMALL-NEXT: fmv.x.w a0, ft0
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@ -67,9 +141,9 @@ define float @lower_constantpool(float %a) nounwind {
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;
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; RV32I-MEDIUM-LABEL: lower_constantpool:
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; RV32I-MEDIUM: # %bb.0:
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; RV32I-MEDIUM-NEXT: .LBB2_1: # Label of block must be emitted
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; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI2_0)
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; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_1)
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; RV32I-MEDIUM-NEXT: .LBB3_1: # Label of block must be emitted
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; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
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; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB3_1)
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; RV32I-MEDIUM-NEXT: flw ft0, 0(a1)
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; RV32I-MEDIUM-NEXT: fmv.w.x ft1, a0
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; RV32I-MEDIUM-NEXT: fadd.s ft0, ft1, ft0
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