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[X86] Fix some clang-tidy bugprone-argument-comment issues
This commit is contained in:
Fangrui Song
parent
074f58db6d
commit
c199a61ffa
@ -2146,7 +2146,7 @@ unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
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SMLoc Start = Tok.getLoc(), End;
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StringRef Identifier = Tok.getString();
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if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
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/*Unevaluated=*/true, End))
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/*IsUnevaluatedOperand=*/true, End))
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return 0;
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if (!Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
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@ -1231,13 +1231,15 @@ bool X86FastISel::X86SelectRet(const Instruction *I) {
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if (SrcVT == MVT::i1) {
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if (Outs[0].Flags.isSExt())
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return false;
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SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
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// TODO
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SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*Op0IsKill=*/false);
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SrcVT = MVT::i8;
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}
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unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
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ISD::SIGN_EXTEND;
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SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
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SrcReg, /*TODO: Kill=*/false);
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// TODO
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SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg,
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/*Op0IsKill=*/false);
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}
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// Make the copy.
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@ -1431,8 +1433,8 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
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ResultReg = createResultReg(&X86::GR32RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0),
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ResultReg);
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ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg, /*Kill=*/true,
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X86::sub_8bit);
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ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg,
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/*Op0IsKill=*/true, X86::sub_8bit);
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if (!ResultReg)
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return false;
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break;
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@ -1555,11 +1557,11 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVZX32rr8),
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Result32).addReg(ResultReg);
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ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, /*Kill=*/true,
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X86::sub_16bit);
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ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32,
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/*Op0IsKill=*/true, X86::sub_16bit);
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} else if (DstVT != MVT::i8) {
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ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
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ResultReg, /*Kill=*/true);
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ResultReg, /*Op0IsKill=*/true);
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if (ResultReg == 0)
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return false;
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}
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@ -1601,11 +1603,11 @@ bool X86FastISel::X86SelectSExt(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVSX32rr8),
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Result32).addReg(ResultReg);
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ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, /*Kill=*/true,
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X86::sub_16bit);
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ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32,
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/*Op0IsKill=*/true, X86::sub_16bit);
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} else if (DstVT != MVT::i8) {
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ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND,
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ResultReg, /*Kill=*/true);
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ResultReg, /*Op0IsKill=*/true);
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if (ResultReg == 0)
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return false;
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}
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@ -1757,7 +1759,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), OpReg)
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.addReg(KOpReg);
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OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Kill=*/true,
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OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Op0IsKill=*/true,
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X86::sub_8bit);
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}
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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@ -1989,7 +1991,7 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) {
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// Now reference the 8-bit subreg of the result.
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ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultSuperReg,
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/*Kill=*/true, X86::sub_8bit);
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/*Op0IsKill=*/true, X86::sub_8bit);
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}
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// Copy the result out of the physreg if we haven't already.
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if (!ResultReg) {
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@ -2103,7 +2105,7 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), CondReg)
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.addReg(KCondReg, getKillRegState(CondIsKill));
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CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true,
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CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Op0IsKill=*/true,
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X86::sub_8bit);
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}
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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@ -2257,12 +2259,12 @@ bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) {
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const TargetRegisterClass *VR128 = &X86::VR128RegClass;
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Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpLHSIsKill,
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CmpRHSReg, CmpRHSIsKill, CC);
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Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, /*IsKill=*/false,
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LHSReg, LHSIsKill);
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Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, /*IsKill=*/true,
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RHSReg, RHSIsKill);
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Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, /*IsKill=*/true,
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AndReg, /*IsKill=*/true);
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Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg,
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/*Op0IsKill=*/false, LHSReg, LHSIsKill);
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Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg,
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/*Op0IsKill=*/true, RHSReg, RHSIsKill);
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Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, /*Op0IsKill=*/true,
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AndReg, /*Op1IsKill=*/true);
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ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg);
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@ -2321,7 +2323,7 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), CondReg)
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.addReg(KCondReg, getKillRegState(CondIsKill));
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CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true,
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CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Op0IsKill=*/true,
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X86::sub_8bit);
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}
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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@ -2578,7 +2580,7 @@ bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM,
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unsigned Reg;
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bool RV = X86FastEmitLoad(VT, SrcAM, nullptr, Reg);
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RV &= X86FastEmitStore(VT, Reg, /*Kill=*/true, DestAM);
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RV &= X86FastEmitStore(VT, Reg, /*ValIsKill=*/true, DestAM);
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assert(RV && "Failed to emit load or store??");
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unsigned Size = VT.getSizeInBits()/8;
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@ -2642,15 +2644,15 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
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assert(Op->getType()->isIntegerTy(16) && "Expected a 16-bit integer!");
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// Explicitly zero-extend the input to 32-bit.
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InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::ZERO_EXTEND, InputReg,
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/*Kill=*/false);
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/*Op0IsKill=*/false);
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// The following SCALAR_TO_VECTOR will be expanded into a VMOVDI2PDIrr.
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InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR,
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InputReg, /*Kill=*/true);
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InputReg, /*Op0IsKill=*/true);
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unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPH2PSZ128rr
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: X86::VCVTPH2PSrr;
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InputReg = fastEmitInst_r(Opc, RC, InputReg, /*Kill=*/true);
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InputReg = fastEmitInst_r(Opc, RC, InputReg, /*Op0IsKill=*/true);
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// The result value is in the lower 32-bits of ResultReg.
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// Emit an explicit copy from register class VR128 to register class FR32.
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@ -3692,10 +3694,10 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
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default: llvm_unreachable("Unexpected value type");
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case MVT::i1:
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case MVT::i8:
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return fastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Kill=*/true,
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return fastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Op0IsKill=*/true,
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X86::sub_8bit);
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case MVT::i16:
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return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Kill=*/true,
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return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Op0IsKill=*/true,
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X86::sub_16bit);
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case MVT::i32:
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return SrcReg;
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@ -3754,7 +3754,7 @@ SDValue X86TargetLowering::LowerFormalArguments(
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// same, so the size of funclets' (mostly empty) frames is dictated by
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// how far this slot is from the bottom (since they allocate just enough
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// space to accommodate holding this slot at the correct offset).
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int PSPSymFI = MFI.CreateStackObject(8, Align(8), /*isSS=*/false);
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int PSPSymFI = MFI.CreateStackObject(8, Align(8), /*isSpillSlot=*/false);
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EHInfo->PSPSymFrameIdx = PSPSymFI;
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}
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}
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@ -24315,7 +24315,8 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
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SDValue VAARG = DAG.getMemIntrinsicNode(
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X86ISD::VAARG_64, dl, VTs, InstOps, MVT::i64, MachinePointerInfo(SV),
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/*Align=*/None, MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
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/*Alignment=*/None,
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MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
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Chain = VAARG.getValue(1);
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// Load the next argument and return it
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