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Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach. llvm-svn: 133940
This commit is contained in:
Owen Anderson
parent
1ae2ca427b
commit
c1dcf312d1
@ -26,11 +26,19 @@ class SubRegIndex {
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string Namespace = "";
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}
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// RegAltNameIndex - The alternate name set to use for register operands of
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// this register class when printing.
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class RegAltNameIndex {
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string Namespace = "";
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}
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def NoRegAltName : RegAltNameIndex;
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// Register - You should define one instance of this class for each register
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// in the target machine. String n will become the "name" of the register.
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class Register<string n> {
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class Register<string n, list<string> altNames = []> {
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string Namespace = "";
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string AsmName = n;
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list<string> AltNames = altNames;
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// Aliases - A list of registers that this register overlaps with. A read or
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// modification of this register can potentially read or modify the aliased
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@ -48,6 +56,10 @@ class Register<string n> {
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// SubRegs.
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list<SubRegIndex> SubRegIndices = [];
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// RegAltNameIndices - The alternate name indices which are valid for this
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// register.
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list<RegAltNameIndex> RegAltNameIndices = [];
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// CompositeIndices - Specify subreg indices that don't correspond directly to
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// a register in SubRegs and are not inherited. The following formats are
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// supported:
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@ -92,7 +104,7 @@ class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
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// registers by register allocators.
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//
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class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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dag regList> {
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dag regList, RegAltNameIndex idx = NoRegAltName> {
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string Namespace = namespace;
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// RegType - Specify the list ValueType of the registers in this register
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@ -124,6 +136,11 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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//
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dag MemberList = regList;
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// AltNameIndex - The alternate register name to use when printing operands
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// of this register class. Every register in the register class must have
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// a valid alternate name for the given index.
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RegAltNameIndex altNameIndex = idx;
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// SubRegClasses - Specify the register class of subregisters as a list of
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// dags: (RegClass SubRegIndex, SubRegindex, ...)
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list<dag> SubRegClasses = [];
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@ -466,6 +483,24 @@ class Operand<ValueType ty> {
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AsmOperandClass ParserMatchClass = ImmAsmOperand;
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}
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class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
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// RegClass - The register class of the operand.
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RegisterClass RegClass = regclass;
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// PrintMethod - The target method to call to print register operands of
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// this type. The method normally will just use an alt-name index to look
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// up the name to print. Default to the generic printOperand().
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string PrintMethod = pm;
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// ParserMatchClass - The "match class" that operands of this type fit
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// in. Match classes are used to define the order in which instructions are
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// match, to ensure that which instructions gets matched is deterministic.
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//
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// The target specific parser must be able to classify an parsed operand into
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// a unique class, which does not partially overlap with any other classes. It
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// can match a subset of some other class, in which case the AsmOperandClass
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// should declare the other operand as one of its super classes.
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AsmOperandClass ParserMatchClass;
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}
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def i1imm : Operand<i1>;
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def i8imm : Operand<i8>;
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def i16imm : Operand<i16>;
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@ -871,6 +871,31 @@ AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
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if (SubOpIdx != -1)
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Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
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if (Rec->isSubClassOf("RegisterOperand")) {
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// RegisterOperand may have an associated ParserMatchClass. If it does,
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// use it, else just fall back to the underlying register class.
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const RecordVal *R = Rec->getValue("ParserMatchClass");
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if (R == 0 || R->getValue() == 0)
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throw "Record `" + Rec->getName() +
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"' does not have a ParserMatchClass!\n";
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if (DefInit *DI= dynamic_cast<DefInit*>(R->getValue())) {
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Record *MatchClass = DI->getDef();
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if (ClassInfo *CI = AsmOperandClasses[MatchClass])
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return CI;
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}
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// No custom match class. Just use the register class.
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Record *ClassRec = Rec->getValueAsDef("RegClass");
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if (!ClassRec)
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throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
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"' has no associated register class!\n");
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if (ClassInfo *CI = RegisterClassClasses[ClassRec])
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return CI;
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throw TGError(Rec->getLoc(), "register class has no class info!");
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}
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if (Rec->isSubClassOf("RegisterClass")) {
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if (ClassInfo *CI = RegisterClassClasses[Rec])
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return CI;
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@ -18,6 +18,7 @@
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "StringToOffsetTable.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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@ -458,6 +459,58 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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O << "}\n";
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}
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static void
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emitRegisterNameString(raw_ostream &O, StringRef AltName,
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const std::vector<CodeGenRegister*> &Registers) {
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StringToOffsetTable StringTable;
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O << " static const unsigned RegAsmOffset" << AltName << "[] = {\n ";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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const CodeGenRegister &Reg = *Registers[i];
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StringRef AsmName;
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// "NoRegAltName" is special. We don't need to do a lookup for that,
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// as it's just a reference to the default register name.
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if (AltName == "" || AltName == "NoRegAltName") {
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AsmName = Reg.TheDef->getValueAsString("AsmName");
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if (AsmName.empty())
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AsmName = Reg.getName();
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} else {
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// Make sure the register has an alternate name for this index.
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std::vector<Record*> AltNameList =
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Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
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unsigned Idx = 0, e;
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for (e = AltNameList.size();
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Idx < e && (AltNameList[Idx]->getName() != AltName);
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++Idx)
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;
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// If the register has an alternate name for this index, use it.
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// Otherwise, leave it empty as an error flag.
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if (Idx < e) {
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std::vector<std::string> AltNames =
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Reg.TheDef->getValueAsListOfStrings("AltNames");
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if (AltNames.size() <= Idx)
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throw TGError(Reg.TheDef->getLoc(),
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(Twine("Register definition missing alt name for '") +
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AltName + "'.").str());
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AsmName = AltNames[Idx];
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}
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}
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O << StringTable.GetOrAddStringOffset(AsmName);
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if (((i + 1) % 14) == 0)
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O << ",\n ";
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else
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O << ", ";
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}
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O << "0\n"
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<< " };\n"
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<< "\n";
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O << " const char *AsmStrs" << AltName << " =\n";
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StringTable.EmitString(O);
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O << ";\n";
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}
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void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
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CodeGenTarget Target(Records);
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@ -465,40 +518,48 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
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std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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const std::vector<CodeGenRegister*> &Registers =
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Target.getRegBank().getRegisters();
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std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
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bool hasAltNames = AltNameIndices.size() > 1;
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StringToOffsetTable StringTable;
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O <<
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"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
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"/// from the register set description. This returns the assembler name\n"
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"/// for the specified register.\n"
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"const char *" << Target.getName() << ClassName
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<< "::getRegisterName(unsigned RegNo) {\n"
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<< " assert(RegNo && RegNo < " << (Registers.size()+1)
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<< " && \"Invalid register number!\");\n"
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<< "\n"
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<< " static const unsigned RegAsmOffset[] = {";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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const CodeGenRegister &Reg = *Registers[i];
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std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
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if (AsmName.empty())
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AsmName = Reg.getName();
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if ((i % 14) == 0)
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O << "\n ";
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O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
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}
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O << "0\n"
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<< " };\n"
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"const char *" << Target.getName() << ClassName << "::";
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if (hasAltNames)
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O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
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else
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O << "getRegisterName(unsigned RegNo) {\n";
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O << " assert(RegNo && RegNo < " << (Registers.size()+1)
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<< " && \"Invalid register number!\");\n"
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<< "\n";
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O << " const char *AsmStrs =\n";
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StringTable.EmitString(O);
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O << ";\n";
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if (hasAltNames) {
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for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i)
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emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
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} else
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emitRegisterNameString(O, "", Registers);
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O << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
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if (hasAltNames) {
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O << " const unsigned *RegAsmOffset;\n"
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<< " const char *AsmStrs;\n"
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<< " switch(AltIdx) {\n"
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<< " default: assert(0 && \"Invalid register alt name index!\");\n";
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for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
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StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace");
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StringRef AltName(AltNameIndices[i]->getName());
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O << " case " << Namespace << "::" << AltName
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<< ":\n"
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<< " AsmStrs = AsmStrs" << AltName << ";\n"
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<< " RegAsmOffset = RegAsmOffset" << AltName << ";\n"
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<< " break;\n";
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}
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O << "}\n";
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}
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O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
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<< " \"Invalid alt name index for register!\");\n"
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<< " return AsmStrs+RegAsmOffset[RegNo-1];\n"
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<< "}\n";
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}
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@ -936,6 +997,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
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const Record *Rec = RO.getRecord();
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StringRef ROName = RO.getName();
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if (Rec->isSubClassOf("RegisterOperand"))
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Rec = Rec->getValueAsDef("RegClass");
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if (Rec->isSubClassOf("RegisterClass")) {
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Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()";
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IAP->addCond(Cond);
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@ -1242,6 +1242,16 @@ TreePatternNode *TreePatternNode::InlinePatternFragments(TreePattern &TP) {
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///
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static EEVT::TypeSet getImplicitType(Record *R, unsigned ResNo,
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bool NotRegisters, TreePattern &TP) {
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// Check to see if this is a register operand.
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if (R->isSubClassOf("RegisterOperand")) {
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assert(ResNo == 0 && "Regoperand ref only has one result!");
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if (NotRegisters)
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return EEVT::TypeSet(); // Unknown.
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Record *RegClass = R->getValueAsDef("RegClass");
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const CodeGenTarget &T = TP.getDAGPatterns().getTargetInfo();
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return EEVT::TypeSet(T.getRegisterClass(RegClass).getValueTypes());
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}
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// Check to see if this is a register or a register class.
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if (R->isSubClassOf("RegisterClass")) {
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assert(ResNo == 0 && "Regclass ref only has one result!");
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@ -1524,6 +1534,11 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
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if (ResultNode->isSubClassOf("PointerLikeRegClass")) {
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MadeChange |= UpdateNodeType(ResNo, MVT::iPTR, TP);
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} else if (ResultNode->isSubClassOf("RegisterOperand")) {
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Record *RegClass = ResultNode->getValueAsDef("RegClass");
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const CodeGenRegisterClass &RC =
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CDP.getTargetInfo().getRegisterClass(RegClass);
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MadeChange |= UpdateNodeType(ResNo, RC.getValueTypes(), TP);
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} else if (ResultNode->getName() == "unknown") {
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// Nothing to do.
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} else {
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@ -1582,6 +1597,11 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
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const CodeGenRegisterClass &RC =
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CDP.getTargetInfo().getRegisterClass(OperandNode);
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MadeChange |= Child->UpdateNodeType(ChildResNo, RC.getValueTypes(), TP);
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} else if (OperandNode->isSubClassOf("RegisterOperand")) {
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Record *RegClass = OperandNode->getValueAsDef("RegClass");
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const CodeGenRegisterClass &RC =
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CDP.getTargetInfo().getRegisterClass(RegClass);
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MadeChange |= Child->UpdateNodeType(ChildResNo, RC.getValueTypes(), TP);
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} else if (OperandNode->isSubClassOf("Operand")) {
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VT = getValueType(OperandNode->getValueAsDef("Type"));
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MadeChange |= Child->UpdateNodeType(ChildResNo, VT, TP);
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@ -1928,7 +1948,8 @@ InferAllTypes(const StringMap<SmallVector<TreePatternNode*,1> > *InNamedTypes) {
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// def : Pat<(v1i64 (bitconvert(v2i32 DPR:$src))), (v1i64 DPR:$src)>;
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if (Nodes[i] == Trees[0] && Nodes[i]->isLeaf()) {
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DefInit *DI = dynamic_cast<DefInit*>(Nodes[i]->getLeafValue());
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if (DI && DI->getDef()->isSubClassOf("RegisterClass"))
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if (DI && (DI->getDef()->isSubClassOf("RegisterClass") ||
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DI->getDef()->isSubClassOf("RegisterOperand")))
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continue;
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}
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@ -2211,7 +2232,8 @@ static bool HandleUse(TreePattern *I, TreePatternNode *Pat,
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if (Pat->getName().empty()) {
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if (Pat->isLeaf()) {
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DefInit *DI = dynamic_cast<DefInit*>(Pat->getLeafValue());
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if (DI && DI->getDef()->isSubClassOf("RegisterClass"))
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if (DI && (DI->getDef()->isSubClassOf("RegisterClass") ||
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DI->getDef()->isSubClassOf("RegisterOperand")))
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I->error("Input " + DI->getDef()->getName() + " must be named!");
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}
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return false;
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@ -2318,6 +2340,7 @@ FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat,
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I->error("set destination should be a register!");
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if (Val->getDef()->isSubClassOf("RegisterClass") ||
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Val->getDef()->isSubClassOf("RegisterOperand") ||
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Val->getDef()->isSubClassOf("PointerLikeRegClass")) {
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if (Dest->getName().empty())
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I->error("set destination must have a name!");
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@ -69,7 +69,9 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
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std::string EncoderMethod;
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unsigned NumOps = 1;
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DagInit *MIOpInfo = 0;
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if (Rec->isSubClassOf("Operand")) {
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if (Rec->isSubClassOf("RegisterOperand")) {
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PrintMethod = Rec->getValueAsString("PrintMethod");
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} else if (Rec->isSubClassOf("Operand")) {
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PrintMethod = Rec->getValueAsString("PrintMethod");
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// If there is an explicit encoder method, use it.
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EncoderMethod = Rec->getValueAsString("EncoderMethod");
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@ -415,6 +417,9 @@ bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
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// Handle explicit registers.
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if (ADI && ADI->getDef()->isSubClassOf("Register")) {
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if (InstOpRec->isSubClassOf("RegisterOperand"))
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InstOpRec = InstOpRec->getValueAsDef("RegClass");
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if (!InstOpRec->isSubClassOf("RegisterClass"))
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return false;
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@ -164,6 +164,11 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
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return *RegBank;
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}
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void CodeGenTarget::ReadRegAltNameIndices() const {
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RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
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std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord());
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}
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
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@ -66,7 +66,9 @@ class CodeGenTarget {
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mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
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mutable CodeGenRegBank *RegBank;
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mutable std::vector<Record*> RegAltNameIndices;
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mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
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void ReadRegAltNameIndices() const;
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void ReadInstructions() const;
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void ReadLegalValueTypes() const;
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@ -100,6 +102,11 @@ public:
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/// return it.
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const CodeGenRegister *getRegisterByName(StringRef Name) const;
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const std::vector<Record*> &getRegAltNameIndices() const {
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if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
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return RegAltNameIndices;
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}
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const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
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return getRegBank().getRegClasses();
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}
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@ -224,6 +224,7 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
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Record *LeafRec = DI->getDef();
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if (// Handle register references. Nothing to do here, they always match.
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LeafRec->isSubClassOf("RegisterClass") ||
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LeafRec->isSubClassOf("RegisterOperand") ||
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LeafRec->isSubClassOf("PointerLikeRegClass") ||
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LeafRec->isSubClassOf("SubRegIndex") ||
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// Place holder for SRCVALUE nodes. Nothing to do here.
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@ -579,15 +580,16 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
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// If this is an explicit register reference, handle it.
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if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
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if (DI->getDef()->isSubClassOf("Register")) {
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Record *Def = DI->getDef();
|
||||
if (Def->isSubClassOf("Register")) {
|
||||
const CodeGenRegister *Reg =
|
||||
CGP.getTargetInfo().getRegBank().getReg(DI->getDef());
|
||||
CGP.getTargetInfo().getRegBank().getReg(Def);
|
||||
AddMatcher(new EmitRegisterMatcher(Reg, N->getType(0)));
|
||||
ResultOps.push_back(NextRecordedOperandNo++);
|
||||
return;
|
||||
}
|
||||
|
||||
if (DI->getDef()->getName() == "zero_reg") {
|
||||
if (Def->getName() == "zero_reg") {
|
||||
AddMatcher(new EmitRegisterMatcher(0, N->getType(0)));
|
||||
ResultOps.push_back(NextRecordedOperandNo++);
|
||||
return;
|
||||
@ -595,16 +597,18 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
|
||||
|
||||
// Handle a reference to a register class. This is used
|
||||
// in COPY_TO_SUBREG instructions.
|
||||
if (DI->getDef()->isSubClassOf("RegisterClass")) {
|
||||
std::string Value = getQualifiedName(DI->getDef()) + "RegClassID";
|
||||
if (Def->isSubClassOf("RegisterOperand"))
|
||||
Def = Def->getValueAsDef("RegClass");
|
||||
if (Def->isSubClassOf("RegisterClass")) {
|
||||
std::string Value = getQualifiedName(Def) + "RegClassID";
|
||||
AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
|
||||
ResultOps.push_back(NextRecordedOperandNo++);
|
||||
return;
|
||||
}
|
||||
|
||||
// Handle a subregister index. This is used for INSERT_SUBREG etc.
|
||||
if (DI->getDef()->isSubClassOf("SubRegIndex")) {
|
||||
std::string Value = getQualifiedName(DI->getDef());
|
||||
if (Def->isSubClassOf("SubRegIndex")) {
|
||||
std::string Value = getQualifiedName(Def);
|
||||
AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
|
||||
ResultOps.push_back(NextRecordedOperandNo++);
|
||||
return;
|
||||
|
||||
@ -248,6 +248,8 @@ struct OperandsSignature {
|
||||
|
||||
// For now, the only other thing we accept is register operands.
|
||||
const CodeGenRegisterClass *RC = 0;
|
||||
if (OpLeafRec->isSubClassOf("RegisterOperand"))
|
||||
OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
|
||||
if (OpLeafRec->isSubClassOf("RegisterClass"))
|
||||
RC = &Target.getRegisterClass(OpLeafRec);
|
||||
else if (OpLeafRec->isSubClassOf("Register"))
|
||||
@ -454,6 +456,8 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
|
||||
std::string SubRegNo;
|
||||
if (Op->getName() != "EXTRACT_SUBREG") {
|
||||
Record *Op0Rec = II.Operands[0].Rec;
|
||||
if (Op0Rec->isSubClassOf("RegisterOperand"))
|
||||
Op0Rec = Op0Rec->getValueAsDef("RegClass");
|
||||
if (!Op0Rec->isSubClassOf("RegisterClass"))
|
||||
continue;
|
||||
DstRC = &Target.getRegisterClass(Op0Rec);
|
||||
|
||||
@ -1305,8 +1305,10 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI,
|
||||
RecordRecTy *Type = dynamic_cast<RecordRecTy*>(TI->getType());
|
||||
Record *TypeRecord = Type->getRecord();
|
||||
bool isReg = false;
|
||||
if (TypeRecord->isSubClassOf("RegisterOperand"))
|
||||
TypeRecord = TypeRecord->getValueAsDef("RegClass");
|
||||
if (TypeRecord->isSubClassOf("RegisterClass")) {
|
||||
Decoder = "Decode" + Type->getRecord()->getName() + "RegisterClass";
|
||||
Decoder = "Decode" + TypeRecord->getName() + "RegisterClass";
|
||||
isReg = true;
|
||||
}
|
||||
|
||||
|
||||
@ -43,10 +43,10 @@ void InstrInfoEmitter::GatherItinClasses() {
|
||||
std::vector<Record*> DefList =
|
||||
Records.getAllDerivedDefinitions("InstrItinClass");
|
||||
std::sort(DefList.begin(), DefList.end(), LessRecord());
|
||||
|
||||
|
||||
for (unsigned i = 0, N = DefList.size(); i < N; i++)
|
||||
ItinClassMap[DefList[i]->getName()] = i;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
|
||||
return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
|
||||
@ -59,7 +59,7 @@ unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
|
||||
std::vector<std::string>
|
||||
InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
std::vector<std::string> Result;
|
||||
|
||||
|
||||
for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
|
||||
// Handle aggregate operands and normal operands the same way by expanding
|
||||
// either case into a list of operands for this op.
|
||||
@ -70,7 +70,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
// operand, which has a single operand, but no declared class for the
|
||||
// operand.
|
||||
DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
|
||||
|
||||
|
||||
if (!MIOI || MIOI->getNumArgs() == 0) {
|
||||
// Single, anonymous, operand.
|
||||
OperandList.push_back(Inst.Operands[i]);
|
||||
@ -86,7 +86,9 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
|
||||
Record *OpR = OperandList[j].Rec;
|
||||
std::string Res;
|
||||
|
||||
|
||||
if (OpR->isSubClassOf("RegisterOperand"))
|
||||
OpR = OpR->getValueAsDef("RegClass");
|
||||
if (OpR->isSubClassOf("RegisterClass"))
|
||||
Res += getQualifiedName(OpR) + "RegClassID, ";
|
||||
else if (OpR->isSubClassOf("PointerLikeRegClass"))
|
||||
@ -94,10 +96,10 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
else
|
||||
// -1 means the operand does not have a fixed register class.
|
||||
Res += "-1, ";
|
||||
|
||||
|
||||
// Fill in applicable flags.
|
||||
Res += "0";
|
||||
|
||||
|
||||
// Ptr value whose register class is resolved via callback.
|
||||
if (OpR->isSubClassOf("PointerLikeRegClass"))
|
||||
Res += "|(1<<TOI::LookupPtrRegClass)";
|
||||
@ -106,7 +108,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
// was of type PredicateOperand.
|
||||
if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
|
||||
Res += "|(1<<TOI::Predicate)";
|
||||
|
||||
|
||||
// Optional def operands. Check to see if the original unexpanded operand
|
||||
// was of type OptionalDefOperand.
|
||||
if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
|
||||
@ -114,7 +116,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
|
||||
// Fill in constraint info.
|
||||
Res += ", ";
|
||||
|
||||
|
||||
const CGIOperandList::ConstraintInfo &Constraint =
|
||||
Inst.Operands[i].Constraints[j];
|
||||
if (Constraint.isNone())
|
||||
@ -126,7 +128,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
Res += "((" + utostr(Constraint.getTiedOperand()) +
|
||||
" << 16) | (1 << TOI::TIED_TO))";
|
||||
}
|
||||
|
||||
|
||||
Result.push_back(Res);
|
||||
}
|
||||
}
|
||||
@ -134,12 +136,12 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
|
||||
return Result;
|
||||
}
|
||||
|
||||
void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
|
||||
void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
|
||||
OperandInfoMapTy &OperandInfoIDs) {
|
||||
// ID #0 is for no operand info.
|
||||
unsigned OperandListNum = 0;
|
||||
OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
|
||||
|
||||
|
||||
OS << "\n";
|
||||
const CodeGenTarget &Target = CDP.getTargetInfo();
|
||||
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
|
||||
@ -147,7 +149,7 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
|
||||
std::vector<std::string> OperandInfo = GetOperandInfo(**II);
|
||||
unsigned &N = OperandInfoIDs[OperandInfo];
|
||||
if (N != 0) continue;
|
||||
|
||||
|
||||
N = ++OperandListNum;
|
||||
OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
|
||||
for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
|
||||
@ -205,7 +207,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
|
||||
std::map<std::vector<Record*>, unsigned> EmittedBarriers;
|
||||
unsigned BarrierNumber = 0;
|
||||
std::map<Record*, unsigned> BarriersMap;
|
||||
|
||||
|
||||
// Emit all of the instruction's implicit uses and defs.
|
||||
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
|
||||
E = Target.inst_end(); II != E; ++II) {
|
||||
@ -231,10 +233,10 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
|
||||
}
|
||||
|
||||
OperandInfoMapTy OperandInfoIDs;
|
||||
|
||||
|
||||
// Emit all of the operand info records.
|
||||
EmitOperandInfo(OS, OperandInfoIDs);
|
||||
|
||||
|
||||
// Emit all of the TargetInstrDesc records in their ENUM ordering.
|
||||
//
|
||||
OS << "\nstatic const TargetInstrDesc " << TargetName
|
||||
|
||||
@ -1443,6 +1443,25 @@ Record::getValueAsListOfInts(StringRef FieldName) const {
|
||||
return Ints;
|
||||
}
|
||||
|
||||
/// getValueAsListOfStrings - This method looks up the specified field and
|
||||
/// returns its value as a vector of strings, throwing an exception if the
|
||||
/// field does not exist or if the value is not the right type.
|
||||
///
|
||||
std::vector<std::string>
|
||||
Record::getValueAsListOfStrings(StringRef FieldName) const {
|
||||
ListInit *List = getValueAsListInit(FieldName);
|
||||
std::vector<std::string> Strings;
|
||||
for (unsigned i = 0; i < List->getSize(); i++) {
|
||||
if (StringInit *II = dynamic_cast<StringInit*>(List->getElement(i))) {
|
||||
Strings.push_back(II->getValue());
|
||||
} else {
|
||||
throw "Record `" + getName() + "', field `" + FieldName.str() +
|
||||
"' does not have a list of strings initializer!";
|
||||
}
|
||||
}
|
||||
return Strings;
|
||||
}
|
||||
|
||||
/// getValueAsDef - This method looks up the specified field and returns its
|
||||
/// value as a Record, throwing an exception if the field does not exist or if
|
||||
/// the value is not the right type.
|
||||
|
||||
@ -1368,6 +1368,12 @@ public:
|
||||
///
|
||||
std::vector<int64_t> getValueAsListOfInts(StringRef FieldName) const;
|
||||
|
||||
/// getValueAsListOfStrings - This method looks up the specified field and
|
||||
/// returns its value as a vector of strings, throwing an exception if the
|
||||
/// field does not exist or if the value is not the right type.
|
||||
///
|
||||
std::vector<std::string> getValueAsListOfStrings(StringRef FieldName) const;
|
||||
|
||||
/// getValueAsDef - This method looks up the specified field and returns its
|
||||
/// value as a Record, throwing an exception if the field does not exist or if
|
||||
/// the value is not the right type.
|
||||
|
||||
@ -112,6 +112,18 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
|
||||
OS << "0 };\n";
|
||||
}
|
||||
|
||||
const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
|
||||
// If the only definition is the default NoRegAltName, we don't need to
|
||||
// emit anything.
|
||||
if (RegAltNameIndices.size() > 1) {
|
||||
OS << "\n// Register alternate name indices\n";
|
||||
OS << "enum {\n";
|
||||
for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
|
||||
OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
|
||||
OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
|
||||
OS << "};\n";
|
||||
}
|
||||
|
||||
// Emit the empty sub-registers list
|
||||
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
|
||||
// Loop over all of the registers which have sub-registers, emitting the
|
||||
|
||||
Loading…
Reference in New Issue
Block a user