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[AArch64] Define subtarget feature strict-align.

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This commit defines subtarget feature strict-align and uses it instead of
cl::opt -aarch64-strict-align to decide whether strict alignment should be
forced.

rdar://problem/21529937

llvm-svn: 243516
This commit is contained in:
Akira Hatanaka 2015-07-29 14:17:26 +00:00
parent 399a1da738
commit c1ecb014d8
7 changed files with 28 additions and 35 deletions
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5
lib/Target/AArch64/AArch64.td
View File

@ -40,6 +40,11 @@ def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
"Has zero-cycle zeroing instructions">;
def FeatureStrictAlign : SubtargetFeature<"strict-align",
"StrictAlign", "true",
"Disallow all unaligned memory "
"access">;
def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
"Reserve X18, making it unavailable "
"as a GPR">;

31
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -40,23 +40,6 @@ using namespace llvm;
STATISTIC(NumTailCalls, "Number of tail calls");
STATISTIC(NumShiftInserts, "Number of vector shift inserts");
namespace {
enum AlignMode {
StrictAlign,
NoStrictAlign
};
}
static cl::opt<AlignMode>
Align(cl::desc("Load/store alignment support"),
cl::Hidden, cl::init(NoStrictAlign),
cl::values(
clEnumValN(StrictAlign, "aarch64-strict-align",
"Disallow all unaligned memory accesses"),
clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
"Allow unaligned memory accesses"),
clEnumValEnd));
// Place holder until extr generation is tested fully.
static cl::opt<bool>
EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
@ -515,8 +498,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setMinFunctionAlignment(2);
RequireStrictAlign = (Align == StrictAlign);
setHasExtractBitsInsn(true);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
@ -787,6 +768,18 @@ MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
return MVT::i64;
}
bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
unsigned AddrSpace,
unsigned Align,
bool *Fast) const {
if (Subtarget->requiresStrictAlign())
return false;
// FIXME: True for Cyclone, but not necessary others.
if (Fast)
*Fast = true;
return true;
}
FastISel *
AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const {

11
lib/Target/AArch64/AArch64ISelLowering.h
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@ -222,8 +222,6 @@ class AArch64Subtarget;
class AArch64TargetMachine;
class AArch64TargetLowering : public TargetLowering {
bool RequireStrictAlign;
public:
explicit AArch64TargetLowering(const TargetMachine &TM,
const AArch64Subtarget &STI);
@ -244,14 +242,7 @@ public:
/// unaligned memory accesses of the specified type.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
unsigned Align = 1,
bool *Fast = nullptr) const override {
if (RequireStrictAlign)
return false;
// FIXME: True for Cyclone, but not necessary others.
if (Fast)
*Fast = true;
return true;
}
bool *Fast = nullptr) const override;
/// LowerOperation - Provide custom lowering hooks for some operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

4
lib/Target/AArch64/AArch64Subtarget.cpp
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@ -48,8 +48,8 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
ReserveX18(false), IsLittle(LittleEndian), CPUString(CPU),
TargetTriple(TT), FrameLowering(),
StrictAlign(false), ReserveX18(false), IsLittle(LittleEndian),
CPUString(CPU), TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
TLInfo(TM, *this) {}

5
lib/Target/AArch64/AArch64Subtarget.h
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@ -51,6 +51,9 @@ protected:
// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
bool HasZeroCycleZeroing;
// StrictAlign - Disallow unaligned memory accesses.
bool StrictAlign;
// ReserveX18 - X18 is not available as a general purpose register.
bool ReserveX18;
@ -104,6 +107,8 @@ public:
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
bool requiresStrictAlign() const { return StrictAlign; }
bool isX18Reserved() const { return ReserveX18; }
bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; }

2
test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
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@ -1,4 +1,4 @@
; RUN: llc -mtriple=arm64-apple-ios -aarch64-strict-align < %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-ios -mattr=+strict-align < %s | FileCheck %s
; Small (16-bytes here) unaligned memcpys should stay memcpy calls if
; strict-alignment is turned on.

5
test/CodeGen/AArch64/arm64-strict-align.ll
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@ -1,7 +1,6 @@
; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-no-strict-align | FileCheck %s
; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-strict-align | FileCheck %s --check-prefix=CHECK-STRICT
; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-strict-align -fast-isel | FileCheck %s --check-prefix=CHECK-STRICT
; RUN: llc < %s -mtriple=arm64-apple-darwin -mattr=+strict-align | FileCheck %s --check-prefix=CHECK-STRICT
; RUN: llc < %s -mtriple=arm64-apple-darwin -mattr=+strict-align -fast-isel | FileCheck %s --check-prefix=CHECK-STRICT
define i32 @f0(i32* nocapture %p) nounwind {
; CHECK-STRICT: ldrh [[HIGH:w[0-9]+]], [x0, #2]