[AArch64][x86] add tests for (v)select bit magic; NFC

llvm-svn: 374334
2025-01-31 20:51:52 +01:00 · 2019-10-10 12:53:24 +00:00 · 2019-10-10 12:53:24 +00:00 · c230251417
commit c230251417
parent 08dec91263
2 changed files with 245 additions and 0 deletions
--- a/test/CodeGen/AArch64/selectcc-to-shiftand.ll
+++ b/test/CodeGen/AArch64/selectcc-to-shiftand.ll
@ -118,3 +118,98 @@ define i32 @PR31175(i32 %x, i32 %y) {
  ret i32 %sel
 }

+define i8 @sel_shift_bool_i8(i1 %t) {
+; CHECK-LABEL: sel_shift_bool_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    tst w0, #0x1
+; CHECK-NEXT:    mov w8, #-128
+; CHECK-NEXT:    csel w0, w8, wzr, ne
+; CHECK-NEXT:    ret
+  %shl = select i1 %t, i8 128, i8 0
+  ret i8 %shl
+}
+
+define i16 @sel_shift_bool_i16(i1 %t) {
+; CHECK-LABEL: sel_shift_bool_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    tst w0, #0x1
+; CHECK-NEXT:    mov w8, #128
+; CHECK-NEXT:    csel w0, w8, wzr, ne
+; CHECK-NEXT:    ret
+  %shl = select i1 %t, i16 128, i16 0
+  ret i16 %shl
+}
+
+define i32 @sel_shift_bool_i32(i1 %t) {
+; CHECK-LABEL: sel_shift_bool_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    tst w0, #0x1
+; CHECK-NEXT:    mov w8, #64
+; CHECK-NEXT:    csel w0, w8, wzr, ne
+; CHECK-NEXT:    ret
+  %shl = select i1 %t, i32 64, i32 0
+  ret i32 %shl
+}
+
+define i64 @sel_shift_bool_i64(i1 %t) {
+; CHECK-LABEL: sel_shift_bool_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    tst w0, #0x1
+; CHECK-NEXT:    mov w8, #65536
+; CHECK-NEXT:    csel x0, x8, xzr, ne
+; CHECK-NEXT:    ret
+  %shl = select i1 %t, i64 65536, i64 0
+  ret i64 %shl
+}
+
+define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
+; CHECK-LABEL: sel_shift_bool_v16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.16b, v0.16b, #7
+; CHECK-NEXT:    sshr v0.16b, v0.16b, #7
+; CHECK-NEXT:    movi v1.16b, #128
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer
+  ret <16 x i8> %shl
+}
+
+define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
+; CHECK-LABEL: sel_shift_bool_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    shl v0.8h, v0.8h, #15
+; CHECK-NEXT:    sshr v0.8h, v0.8h, #15
+; CHECK-NEXT:    movi v1.8h, #128
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer
+  ret <8 x i16> %shl
+}
+
+define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
+; CHECK-LABEL: sel_shift_bool_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    shl v0.4s, v0.4s, #31
+; CHECK-NEXT:    sshr v0.4s, v0.4s, #31
+; CHECK-NEXT:    movi v1.4s, #64
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer
+  ret <4 x i32> %shl
+}
+
+define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {
+; CHECK-LABEL: sel_shift_bool_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    mov w8, #65536
+; CHECK-NEXT:    shl v0.2d, v0.2d, #63
+; CHECK-NEXT:    sshr v0.2d, v0.2d, #63
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer
+  ret <2 x i64> %shl
+}
--- a/test/CodeGen/X86/selectcc-to-shiftand.ll
+++ b/test/CodeGen/X86/selectcc-to-shiftand.ll
@ -198,3 +198,153 @@ define i32 @PR31175(i32 %x, i32 %y) {
  %sel = select i1 %cmp, i32 %sub, i32 0
  ret i32 %sel
 }
+
+define i8 @sel_shift_bool_i8(i1 %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_i8:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NOBMI-NEXT:    notb %dil
+; CHECK-NOBMI-NEXT:    shlb $7, %dil
+; CHECK-NOBMI-NEXT:    leal -128(%rdi), %eax
+; CHECK-NOBMI-NEXT:    # kill: def $al killed $al killed $eax
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_i8:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-BMI-NEXT:    notb %dil
+; CHECK-BMI-NEXT:    shlb $7, %dil
+; CHECK-BMI-NEXT:    leal -128(%rdi), %eax
+; CHECK-BMI-NEXT:    # kill: def $al killed $al killed $eax
+; CHECK-BMI-NEXT:    retq
+  %shl = select i1 %t, i8 128, i8 0
+  ret i8 %shl
+}
+
+define i16 @sel_shift_bool_i16(i1 %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_i16:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    movl %edi, %eax
+; CHECK-NOBMI-NEXT:    andl $1, %eax
+; CHECK-NOBMI-NEXT:    shll $7, %eax
+; CHECK-NOBMI-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_i16:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    movl %edi, %eax
+; CHECK-BMI-NEXT:    andl $1, %eax
+; CHECK-BMI-NEXT:    shll $7, %eax
+; CHECK-BMI-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-BMI-NEXT:    retq
+  %shl = select i1 %t, i16 128, i16 0
+  ret i16 %shl
+}
+
+define i32 @sel_shift_bool_i32(i1 %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_i32:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    movl %edi, %eax
+; CHECK-NOBMI-NEXT:    andl $1, %eax
+; CHECK-NOBMI-NEXT:    shll $6, %eax
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_i32:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    movl %edi, %eax
+; CHECK-BMI-NEXT:    andl $1, %eax
+; CHECK-BMI-NEXT:    shll $6, %eax
+; CHECK-BMI-NEXT:    retq
+  %shl = select i1 %t, i32 64, i32 0
+  ret i32 %shl
+}
+
+define i64 @sel_shift_bool_i64(i1 %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_i64:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    movl %edi, %eax
+; CHECK-NOBMI-NEXT:    andl $1, %eax
+; CHECK-NOBMI-NEXT:    shlq $16, %rax
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_i64:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    movl %edi, %eax
+; CHECK-BMI-NEXT:    andl $1, %eax
+; CHECK-BMI-NEXT:    shlq $16, %rax
+; CHECK-BMI-NEXT:    retq
+  %shl = select i1 %t, i64 65536, i64 0
+  ret i64 %shl
+}
+
+define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_v16i8:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    psllw $7, %xmm0
+; CHECK-NOBMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_v16i8:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    psllw $7, %xmm0
+; CHECK-BMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-BMI-NEXT:    retq
+  %shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer
+  ret <16 x i8> %shl
+}
+
+define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_v8i16:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    psllw $15, %xmm0
+; CHECK-NOBMI-NEXT:    psraw $15, %xmm0
+; CHECK-NOBMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_v8i16:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    psllw $15, %xmm0
+; CHECK-BMI-NEXT:    psraw $15, %xmm0
+; CHECK-BMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-BMI-NEXT:    retq
+  %shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer
+  ret <8 x i16> %shl
+}
+
+define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_v4i32:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    pslld $31, %xmm0
+; CHECK-NOBMI-NEXT:    psrad $31, %xmm0
+; CHECK-NOBMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_v4i32:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    pslld $31, %xmm0
+; CHECK-BMI-NEXT:    psrad $31, %xmm0
+; CHECK-BMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-BMI-NEXT:    retq
+  %shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer
+  ret <4 x i32> %shl
+}
+
+define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {
+; CHECK-NOBMI-LABEL: sel_shift_bool_v2i64:
+; CHECK-NOBMI:       # %bb.0:
+; CHECK-NOBMI-NEXT:    psllq $63, %xmm0
+; CHECK-NOBMI-NEXT:    psrad $31, %xmm0
+; CHECK-NOBMI-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-NOBMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-NOBMI-NEXT:    retq
+;
+; CHECK-BMI-LABEL: sel_shift_bool_v2i64:
+; CHECK-BMI:       # %bb.0:
+; CHECK-BMI-NEXT:    psllq $63, %xmm0
+; CHECK-BMI-NEXT:    psrad $31, %xmm0
+; CHECK-BMI-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; CHECK-BMI-NEXT:    pand {{.*}}(%rip), %xmm0
+; CHECK-BMI-NEXT:    retq
+  %shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer
+  ret <2 x i64> %shl
+}