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[TableGen] Fix leaking of PhysRegInputs.

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Instead of dynamically allocating the vector for PhysRegs, we can
allocate it on the stack and move it into InstructionMemo.

Reviewers: mcrosier, craig.topper, RKSimon, dsanders

Reviewed By: dsanders

Differential Revision: https://reviews.llvm.org/D47461

llvm-svn: 333438
This commit is contained in:
Florian Hahn 2018-05-29 17:40:03 +00:00
parent 93eb7c4e2b
commit c24f7d921e
1 changed files with 17 additions and 13 deletions
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30
utils/TableGen/FastISelEmitter.cpp
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@ -36,8 +36,12 @@ struct InstructionMemo {
std::string Name;
const CodeGenRegisterClass *RC;
std::string SubRegNo;
std::vector<std::string>* PhysRegs;
std::vector<std::string> PhysRegs;
std::string PredicateCheck;
// Make sure we do not copy InstructionMemo.
InstructionMemo(const InstructionMemo &Other) = delete;
InstructionMemo(InstructionMemo &&Other) = default;
};
} // End anonymous namespace
@ -527,10 +531,10 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
DstRC))
continue;
std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
std::vector<std::string> PhysRegInputs;
if (InstPatNode->getOperator()->getName() == "imm" ||
InstPatNode->getOperator()->getName() == "fpimm")
PhysRegInputs->push_back("");
PhysRegInputs.push_back("");
else {
// Compute the PhysRegs used by the given pattern, and check that
// the mapping from the src to dst patterns is simple.
@ -548,7 +552,7 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
++DstIndex;
}
PhysRegInputs->push_back(PhysReg);
PhysRegInputs.push_back(PhysReg);
}
if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
@ -592,8 +596,8 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
// Note: Instructions with the same complexity will appear in the order
// that they are encountered.
SimplePatterns[Operands][OpcodeName][VT][RetVT].insert(
std::make_pair(complexity, Memo));
SimplePatterns[Operands][OpcodeName][VT][RetVT].emplace(complexity,
std::move(Memo));
// If any of the operands were immediates with predicates on them, strip
// them down to a signature that doesn't have predicates so that we can
@ -648,22 +652,22 @@ void FastISelMap::emitInstructionCode(raw_ostream &OS,
OS << " ";
}
for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
if ((*Memo.PhysRegs)[i] != "")
for (unsigned i = 0; i < Memo.PhysRegs.size(); ++i) {
if (Memo.PhysRegs[i] != "")
OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
<< "TII.get(TargetOpcode::COPY), "
<< (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
<< "TII.get(TargetOpcode::COPY), " << Memo.PhysRegs[i]
<< ").addReg(Op" << i << ");\n";
}
OS << " return fastEmitInst_";
if (Memo.SubRegNo.empty()) {
Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
ImmediatePredicates, true);
Operands.PrintManglingSuffix(OS, Memo.PhysRegs, ImmediatePredicates,
true);
OS << "(" << InstNS << "::" << Memo.Name << ", ";
OS << "&" << InstNS << "::" << Memo.RC->getName() << "RegClass";
if (!Operands.empty())
OS << ", ";
Operands.PrintArguments(OS, *Memo.PhysRegs);
Operands.PrintArguments(OS, Memo.PhysRegs);
OS << ");\n";
} else {
OS << "extractsubreg(" << RetVTName