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[IRCE] Canonicalize pre/post loops after the blocks are added into parent loop
Summary: We were canonizalizing the pre loop (into loop-simplify form) before the post loop blocks were added into parent loop. This is incorrect when IRCE is done on a subloop. The post-loop blocks are created, but not yet added to the parent loop. So, loop-simplification on the pre-loop incorrectly updates LoopInfo. This patch corrects the ordering so that pre and post loop blocks are added to parent loop (if any), and then the loops are canonicalized to LCSSA and LoopSimplifyForm. Reviewers: reames, sanjoy, apilipenko Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33846 llvm-svn: 304800
This commit is contained in:
Anna Thomas
parent
0ed1e4f769
commit
c26a4baf9a
@ -1371,28 +1371,35 @@ bool LoopConstrainer::run() {
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DT.recalculate(F);
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// We need to first add all the pre and post loop blocks into the loop
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// structures (as part of createClonedLoopStructure), and then update the
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// LCSSA form and LoopSimplifyForm. This is necessary for correctly updating
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// LI when LoopSimplifyForm is generated.
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Loop *PreL = nullptr, *PostL = nullptr;
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if (!PreLoop.Blocks.empty()) {
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auto *L = createClonedLoopStructure(
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PreL = createClonedLoopStructure(
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&OriginalLoop, OriginalLoop.getParentLoop(), PreLoop.Map);
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formLCSSARecursively(*L, DT, &LI, &SE);
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simplifyLoop(L, &DT, &LI, &SE, nullptr, true);
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// Pre loops are slow paths, we do not need to perform any loop
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// optimizations on them.
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DisableAllLoopOptsOnLoop(*L);
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}
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if (!PostLoop.Blocks.empty()) {
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auto *L = createClonedLoopStructure(
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PostL = createClonedLoopStructure(
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&OriginalLoop, OriginalLoop.getParentLoop(), PostLoop.Map);
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formLCSSARecursively(*L, DT, &LI, &SE);
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simplifyLoop(L, &DT, &LI, &SE, nullptr, true);
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// Post loops are slow paths, we do not need to perform any loop
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// optimizations on them.
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DisableAllLoopOptsOnLoop(*L);
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}
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formLCSSARecursively(OriginalLoop, DT, &LI, &SE);
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simplifyLoop(&OriginalLoop, &DT, &LI, &SE, nullptr, true);
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// This function canonicalizes the loop into Loop-Simplify and LCSSA forms.
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auto CanonicalizeLoop = [&] (Loop *L, bool IsOriginalLoop) {
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formLCSSARecursively(*L, DT, &LI, &SE);
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simplifyLoop(L, &DT, &LI, &SE, nullptr, true);
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// Pre/post loops are slow paths, we do not need to perform any loop
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// optimizations on them.
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if (!IsOriginalLoop)
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DisableAllLoopOptsOnLoop(*L);
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};
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if (PreL)
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CanonicalizeLoop(PreL, false);
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if (PostL)
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CanonicalizeLoop(PostL, false);
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CanonicalizeLoop(&OriginalLoop, true);
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return true;
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}
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182
test/Transforms/IRCE/correct-loop-info.ll
Normal file
182
test/Transforms/IRCE/correct-loop-info.ll
Normal file
@ -0,0 +1,182 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -irce < %s -S | FileCheck %s
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; REQUIRES: asserts
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; IRCE creates the pre and post loop, and invokes the
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; canonicalizing these loops to LCSSA and loop-simplfy structure. Make sure that the update to the loopinfo does not
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; incorrectly change the header while canonicalizing these pre/post loops. We
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; were incorrectly updating LI when the split loop is a subloop as in the case below.
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source_filename = "correct-loop-info.ll"
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define void @baz() personality i32* ()* @ham {
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; CHECK-LABEL: @baz(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[OUTERHEADER:%.*]]
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; CHECK: outerheader:
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; CHECK-NEXT: [[TMP:%.*]] = icmp slt i32 undef, 84
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; CHECK-NEXT: br i1 [[TMP]], label [[BB2:%.*]], label [[BB16:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: br i1 false, label [[INNERHEADER_PRELOOP_PREHEADER:%.*]], label [[PRELOOP_PSEUDO_EXIT:%.*]]
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; CHECK: innerheader.preloop.preheader:
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; CHECK-NEXT: br label [[INNERHEADER_PRELOOP:%.*]]
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; CHECK: mainloop:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i32 [[INDVAR_END:%.*]], -1
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; CHECK-NEXT: br i1 [[TMP0]], label [[INNERHEADER_PREHEADER:%.*]], label [[MAIN_PSEUDO_EXIT:%.*]]
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; CHECK: innerheader.preheader:
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; CHECK-NEXT: br label [[INNERHEADER:%.*]]
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; CHECK: innerheader:
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; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP6:%.*]], [[BB8:%.*]] ], [ [[TMP4_PRELOOP_COPY:%.*]], [[INNERHEADER_PREHEADER]] ]
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; CHECK-NEXT: invoke void @pluto()
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; CHECK-NEXT: to label [[BB5:%.*]] unwind label %outer_exiting.loopexit.split-lp.loopexit.split-lp
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; CHECK: bb5:
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; CHECK-NEXT: [[TMP6]] = add i32 [[TMP4]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 0
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; CHECK-NEXT: br i1 true, label [[BB8]], label [[EXIT3_LOOPEXIT5:%.*]]
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; CHECK: bb8:
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; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP6]], 84
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP6]], -1
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; CHECK-NEXT: br i1 [[TMP1]], label [[INNERHEADER]], label [[MAIN_EXIT_SELECTOR:%.*]]
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; CHECK: main.exit.selector:
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; CHECK-NEXT: [[TMP6_LCSSA:%.*]] = phi i32 [ [[TMP6]], [[BB8]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP6_LCSSA]], 84
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; CHECK-NEXT: br i1 [[TMP2]], label [[MAIN_PSEUDO_EXIT]], label [[BB13:%.*]]
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; CHECK: main.pseudo.exit:
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; CHECK-NEXT: [[TMP4_COPY:%.*]] = phi i32 [ [[TMP4_PRELOOP_COPY]], [[MAINLOOP:%.*]] ], [ [[TMP6_LCSSA]], [[MAIN_EXIT_SELECTOR]] ]
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; CHECK-NEXT: [[INDVAR_END1:%.*]] = phi i32 [ [[INDVAR_END]], [[MAINLOOP]] ], [ [[TMP6_LCSSA]], [[MAIN_EXIT_SELECTOR]] ]
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; CHECK-NEXT: br label [[POSTLOOP:%.*]]
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; CHECK: outer_exiting.loopexit:
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; CHECK-NEXT: [[LPAD_LOOPEXIT:%.*]] = landingpad { i8*, i32 }
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; CHECK-NEXT: cleanup
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; CHECK-NEXT: br label [[OUTER_EXITING:%.*]]
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; CHECK: outer_exiting.loopexit.split-lp.loopexit:
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; CHECK-NEXT: [[LPAD_LOOPEXIT2:%.*]] = landingpad { i8*, i32 }
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; CHECK-NEXT: cleanup
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; CHECK-NEXT: br label %outer_exiting.loopexit.split-lp
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; CHECK: outer_exiting.loopexit.split-lp.loopexit.split-lp:
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; CHECK-NEXT: %lpad.loopexit.split-lp3 = landingpad { i8*, i32 }
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; CHECK-NEXT: cleanup
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; CHECK-NEXT: br label %outer_exiting.loopexit.split-lp
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; CHECK: outer_exiting.loopexit.split-lp:
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; CHECK-NEXT: br label [[OUTER_EXITING]]
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; CHECK: outer_exiting:
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; CHECK-NEXT: switch i32 undef, label [[EXIT2:%.*]] [
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; CHECK-NEXT: i32 142, label [[BB14:%.*]]
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; CHECK-NEXT: i32 448, label [[EXIT:%.*]]
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; CHECK-NEXT: ]
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; CHECK: exit3.loopexit:
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; CHECK-NEXT: br label [[EXIT3:%.*]]
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; CHECK: exit3.loopexit4:
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; CHECK-NEXT: br label [[EXIT3]]
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; CHECK: exit3.loopexit5:
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; CHECK-NEXT: br label [[EXIT3]]
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; CHECK: exit3:
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; CHECK-NEXT: ret void
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; CHECK: bb13.loopexit:
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; CHECK-NEXT: br label [[BB13]]
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; CHECK: bb13:
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; CHECK-NEXT: unreachable
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; CHECK: bb14:
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; CHECK-NEXT: br label [[OUTERHEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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; CHECK: bb16:
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; CHECK-NEXT: ret void
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; CHECK: exit2:
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; CHECK-NEXT: ret void
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; CHECK: innerheader.preloop:
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; CHECK-NEXT: [[TMP4_PRELOOP:%.*]] = phi i32 [ [[TMP6_PRELOOP:%.*]], [[BB8_PRELOOP:%.*]] ], [ undef, [[INNERHEADER_PRELOOP_PREHEADER]] ]
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; CHECK-NEXT: invoke void @pluto()
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; CHECK-NEXT: to label [[BB5_PRELOOP:%.*]] unwind label [[OUTER_EXITING_LOOPEXIT:%.*]]
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; CHECK: bb5.preloop:
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; CHECK-NEXT: [[TMP6_PRELOOP]] = add i32 [[TMP4_PRELOOP]], 1
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; CHECK-NEXT: [[TMP7_PRELOOP:%.*]] = icmp ult i32 [[TMP6_PRELOOP]], 0
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; CHECK-NEXT: br i1 [[TMP7_PRELOOP]], label [[BB8_PRELOOP]], label [[EXIT3_LOOPEXIT:%.*]]
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; CHECK: bb8.preloop:
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; CHECK-NEXT: [[TMP9_PRELOOP:%.*]] = icmp slt i32 [[TMP6_PRELOOP]], 84
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; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP6_PRELOOP]], -1
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; CHECK-NEXT: br i1 [[TMP3]], label [[INNERHEADER_PRELOOP]], label [[PRELOOP_EXIT_SELECTOR:%.*]], !llvm.loop !0, !irce.loop.clone !5
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; CHECK: preloop.exit.selector:
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; CHECK-NEXT: [[TMP6_PRELOOP_LCSSA:%.*]] = phi i32 [ [[TMP6_PRELOOP]], [[BB8_PRELOOP]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP6_PRELOOP_LCSSA]], 84
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; CHECK-NEXT: br i1 [[TMP4]], label [[PRELOOP_PSEUDO_EXIT]], label [[BB13]]
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; CHECK: preloop.pseudo.exit:
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; CHECK-NEXT: [[TMP4_PRELOOP_COPY]] = phi i32 [ undef, [[BB2]] ], [ [[TMP6_PRELOOP_LCSSA]], [[PRELOOP_EXIT_SELECTOR]] ]
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; CHECK-NEXT: [[INDVAR_END]] = phi i32 [ undef, [[BB2]] ], [ [[TMP6_PRELOOP_LCSSA]], [[PRELOOP_EXIT_SELECTOR]] ]
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; CHECK-NEXT: br label [[MAINLOOP]]
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; CHECK: postloop:
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; CHECK-NEXT: br label [[INNERHEADER_POSTLOOP:%.*]]
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; CHECK: innerheader.postloop:
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; CHECK-NEXT: [[TMP4_POSTLOOP:%.*]] = phi i32 [ [[TMP6_POSTLOOP:%.*]], [[BB8_POSTLOOP:%.*]] ], [ [[TMP4_COPY]], [[POSTLOOP]] ]
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; CHECK-NEXT: invoke void @pluto()
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; CHECK-NEXT: to label [[BB5_POSTLOOP:%.*]] unwind label %outer_exiting.loopexit.split-lp.loopexit
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; CHECK: bb5.postloop:
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; CHECK-NEXT: [[TMP6_POSTLOOP]] = add i32 [[TMP4_POSTLOOP]], 1
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; CHECK-NEXT: [[TMP7_POSTLOOP:%.*]] = icmp ult i32 [[TMP6_POSTLOOP]], 0
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; CHECK-NEXT: br i1 [[TMP7_POSTLOOP]], label [[BB8_POSTLOOP]], label [[EXIT3_LOOPEXIT4:%.*]]
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; CHECK: bb8.postloop:
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; CHECK-NEXT: [[TMP9_POSTLOOP:%.*]] = icmp slt i32 [[TMP6_POSTLOOP]], 84
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; CHECK-NEXT: br i1 [[TMP9_POSTLOOP]], label [[INNERHEADER_POSTLOOP]], label [[BB13_LOOPEXIT:%.*]], !llvm.loop !6, !irce.loop.clone !5
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;
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bb:
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br label %outerheader
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outerheader: ; preds = %bb14, %bb
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%tmp = icmp slt i32 undef, 84
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br i1 %tmp, label %bb2, label %bb16
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bb2: ; preds = %outerheader
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br label %innerheader
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innerheader: ; preds = %bb8, %bb2
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%tmp4 = phi i32 [ %tmp6, %bb8 ], [ undef, %bb2 ]
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invoke void @pluto()
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to label %bb5 unwind label %outer_exiting
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bb5: ; preds = %innerheader
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%tmp6 = add i32 %tmp4, 1
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%tmp7 = icmp ult i32 %tmp6, 0
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br i1 %tmp7, label %bb8, label %exit3
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bb8: ; preds = %bb5
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%tmp9 = icmp slt i32 %tmp6, 84
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br i1 %tmp9, label %innerheader, label %bb13
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outer_exiting: ; preds = %innerheader
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%tmp11 = landingpad { i8*, i32 }
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cleanup
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switch i32 undef, label %exit2 [
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i32 142, label %bb14
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i32 448, label %exit
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]
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exit3: ; preds = %bb5
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ret void
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bb13: ; preds = %bb8
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unreachable
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bb14: ; preds = %outer_exiting
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br label %outerheader
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exit: ; preds = %outer_exiting
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ret void
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bb16: ; preds = %outerheader
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ret void
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exit2: ; preds = %outer_exiting
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ret void
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}
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declare i32* @ham()
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declare void @pluto()
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!0 = distinct !{!0, !1, !2, !3, !4}
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!1 = !{!"llvm.loop.unroll.disable"}
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!2 = !{!"llvm.loop.vectorize.enable", i1 false}
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!3 = !{!"llvm.loop.licm_versioning.disable"}
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!4 = !{!"llvm.loop.distribute.enable", i1 false}
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!5 = !{}
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!6 = distinct !{!6, !1, !2, !3, !4}
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