mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
[ARM][LowOverheadLoops] Revert after read/write
Currently we check whether LR is stored/loaded to/from inbetween the
loop decrement and loop end pseudo instructions. There's two problems
here:
- It relies on all load/store instructions being labelled as such in
tablegen.
- Actually any use of loop decrement is troublesome because the value
doesn't exist!
So we need to check for any read/write of LR that occurs between the
two instructions and revert if we find anything.
Differential Revision: https://reviews.llvm.org/D65792
llvm-svn: 368130
This commit is contained in:
Sam Parker
parent
b9b91527c5
commit
c289d4459d
@ -11,8 +11,7 @@
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/// The expectation is that the loop contains three pseudo instructions:
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/// - t2*LoopStart - placed in the preheader or pre-preheader. The do-loop
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/// form should be in the preheader, whereas the while form should be in the
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/// preheaders only predecessor. TODO: Could DoLoopStart get moved into the
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/// pre-preheader?
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/// preheaders only predecessor.
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/// - t2LoopDec - placed within in the loop body.
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/// - t2LoopEnd - the loop latch terminator.
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///
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@ -176,19 +175,25 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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// faster than performing a sub,cmp,br or even subs,br.
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Revert = true;
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if (!Dec)
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if (!Dec || End)
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continue;
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// If we find that we load/store LR between LoopDec and LoopEnd, expect
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// that the decremented value has been spilled to the stack. Because
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// this value isn't actually going to be produced until the latch, by LE,
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// we would need to generate a real sub. The value is also likely to be
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// reloaded for use of LoopEnd - in which in case we'd need to perform
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// an add because it gets negated again by LE! The other option is to
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// then generate the other form of LE which doesn't perform the sub.
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if (MI.mayLoad() || MI.mayStore())
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Revert =
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MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == ARM::LR;
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// If we find that LR has been written or read between LoopDec and
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// LoopEnd, expect that the decremented value is being used else where.
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// Because this value isn't actually going to be produced until the
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// latch, by LE, we would need to generate a real sub. The value is also
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// likely to be copied/reloaded for use of LoopEnd - in which in case
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// we'd need to perform an add because it gets subtracted again by LE!
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// The other option is to then generate the other form of LE which doesn't
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// perform the sub.
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for (auto &MO : MI.operands()) {
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if (MI.getOpcode() != ARM::t2LoopDec && MO.isReg() &&
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MO.getReg() == ARM::LR) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Found LR Use/Def: " << MI);
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Revert = true;
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break;
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}
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}
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}
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if (Dec && End && Revert)
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128
test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir
Normal file
128
test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir
Normal file
@ -0,0 +1,128 @@
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# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
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# CHECK: while.body:
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# CHECK-NOT: t2DLS
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# CHECK-NOT: t2LEUpdate
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--- |
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define i32 @mov_between_dec_end(i32 %n) #0 {
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entry:
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%cmp6 = icmp eq i32 %n, 0
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br i1 %cmp6, label %while.end, label %while.body.preheader
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while.body.preheader: ; preds = %entry
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call void @llvm.set.loop.iterations.i32(i32 %n)
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br label %while.body
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while.body: ; preds = %while.body, %while.body.preheader
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%res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]
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%0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]
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%1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
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%add = add i32 %1, 0
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%2 = icmp ne i32 %1, 0
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br i1 %2, label %while.body, label %while.end
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while.end: ; preds = %while.body, %entry
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%res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]
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ret i32 %res.0.lcssa
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}
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; Function Attrs: noduplicate nounwind
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declare void @llvm.set.loop.iterations.i32(i32) #1
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
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attributes #0 = { "target-features"="+mve.fp" }
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attributes #1 = { noduplicate nounwind }
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attributes #2 = { nounwind }
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...
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---
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name: mov_between_dec_end
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: false
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 16
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.4(0x30000000), %bb.1(0x50000000)
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frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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frame-setup CFI_INSTRUCTION offset $r5, -12
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frame-setup CFI_INSTRUCTION offset $r4, -16
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tCBZ $r0, %bb.4
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bb.1.while.body.preheader:
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successors: %bb.2(0x80000000)
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$lr = tMOVr $r0, 14, $noreg
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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t2DoLoopStart killed $r0
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bb.2.while.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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renamable $r4 = tMOVr $lr, 14, $noreg
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t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3.while.end:
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$r0 = tMOVr killed $r4, 14, $noreg
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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bb.4:
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = tMOVr killed $r4, 14, $noreg
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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...
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128
test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir
Normal file
128
test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir
Normal file
@ -0,0 +1,128 @@
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# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
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# CHECK: while.body:
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# CHECK-NOT: t2DLS
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# CHECK-NOT: t2LEUpdate
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--- |
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define i32 @mov_between_dec_end(i32 %n) #0 {
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entry:
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%cmp6 = icmp eq i32 %n, 0
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br i1 %cmp6, label %while.end, label %while.body.preheader
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while.body.preheader: ; preds = %entry
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call void @llvm.set.loop.iterations.i32(i32 %n)
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br label %while.body
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while.body: ; preds = %while.body, %while.body.preheader
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%res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]
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%0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ]
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%1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
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%add = add i32 %1, 2
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%2 = icmp ne i32 %1, 0
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br i1 %2, label %while.body, label %while.end
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while.end: ; preds = %while.body, %entry
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%res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]
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ret i32 %res.0.lcssa
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}
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; Function Attrs: noduplicate nounwind
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declare void @llvm.set.loop.iterations.i32(i32) #1
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
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attributes #0 = { "target-features"="+mve.fp" }
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attributes #1 = { noduplicate nounwind }
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attributes #2 = { nounwind }
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...
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---
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name: mov_between_dec_end
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: false
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 16
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.4(0x30000000), %bb.1(0x50000000)
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frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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frame-setup CFI_INSTRUCTION offset $r5, -12
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frame-setup CFI_INSTRUCTION offset $r4, -16
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tCBZ $r0, %bb.4
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bb.1.while.body.preheader:
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successors: %bb.2(0x80000000)
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$lr = tMOVr $r0, 14, $noreg
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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t2DoLoopStart killed $r0
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bb.2.while.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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$r4 = tMOVr $lr, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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$lr = tMOVr $r4, 14, $noreg
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t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3.while.end:
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$r0 = tMOVr killed $r4, 14, $noreg
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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bb.4:
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = tMOVr killed $r4, 14, $noreg
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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...
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