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Add a transform to DAG Combiner. This improves the
code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. llvm-svn: 122090
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@ -3171,6 +3171,26 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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DAG.getConstant(c1 + c2, N1.getValueType()));
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}
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// fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
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// This is only valid if the OpSizeInBits + c1 = size of inner shift
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if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
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N0.getOperand(0).getOpcode() == ISD::SRL &&
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N0.getOperand(0)->getOperand(1).getOpcode() == ISD::Constant) {
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uint64_t c1 =
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cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
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uint64_t c2 = N1C->getZExtValue();
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EVT InnerShiftVT = N0.getOperand(0)->getOperand(1).getValueType();
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uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
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if (c1 + OpSizeInBits == InnerShiftSize) {
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if (c1 + c2 >= InnerShiftSize)
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return DAG.getConstant(0, VT);
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return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
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DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
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N0.getOperand(0)->getOperand(0),
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DAG.getConstant(c1 + c2, InnerShiftVT)));
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}
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}
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// fold (srl (shl x, c), c) -> (and x, cst2)
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if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
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N0.getValueSizeInBits() <= 64) {
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9
test/CodeGen/X86/x86_64-mul-by-const.ll
Normal file
9
test/CodeGen/X86/x86_64-mul-by-const.ll
Normal file
@ -0,0 +1,9 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; Formerly there were two shifts. 8771012.
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define i32 @f9188_mul365384439_shift27(i32 %A) nounwind {
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; CHECK: imulq $365384439,
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; CHECK: shrq $59, %rax
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%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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