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https://github.com/RPCS3/llvm-mirror.git
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Add code for analyzing FP branches. Clean up branch Analysis functions.
llvm-svn: 128718
This commit is contained in:
Akira Hatanaka
parent
aff6a9e50a
commit
c2d74b05ca
@ -218,103 +218,42 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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/// GetCondFromBranchOpc - Return the Mips CC that matches
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/// the correspondent Branch instruction opcode.
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static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
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{
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switch (BrOpc) {
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default: return Mips::COND_INVALID;
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case Mips::BEQ : return Mips::COND_E;
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case Mips::BNE : return Mips::COND_NE;
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case Mips::BGTZ : return Mips::COND_GZ;
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case Mips::BGEZ : return Mips::COND_GEZ;
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case Mips::BLTZ : return Mips::COND_LZ;
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case Mips::BLEZ : return Mips::COND_LEZ;
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static unsigned GetAnalyzableBrOpc(unsigned Opc) {
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return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
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Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
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Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? Opc : 0;
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}
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// We dont do fp branch analysis yet!
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case Mips::BC1T :
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case Mips::BC1F : return Mips::COND_INVALID;
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
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{
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BEQ : return Mips::BNE;
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case Mips::BNE : return Mips::BEQ;
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case Mips::BGTZ : return Mips::BLEZ;
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case Mips::BGEZ : return Mips::BLTZ;
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case Mips::BLTZ : return Mips::BGEZ;
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case Mips::BLEZ : return Mips::BGTZ;
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case Mips::BC1T : return Mips::BC1F;
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case Mips::BC1F : return Mips::BC1T;
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}
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}
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/// GetCondBranchFromCond - Return the Branch instruction
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/// opcode that matches the cc.
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unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
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{
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case Mips::COND_E : return Mips::BEQ;
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case Mips::COND_NE : return Mips::BNE;
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case Mips::COND_GZ : return Mips::BGTZ;
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case Mips::COND_GEZ : return Mips::BGEZ;
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case Mips::COND_LZ : return Mips::BLTZ;
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case Mips::COND_LEZ : return Mips::BLEZ;
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static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand>& Cond) {
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assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
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int NumOp = Inst->getNumExplicitOperands();
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// for both int and fp branches, the last explicit operand is the
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// MBB.
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BB = Inst->getOperand(NumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(Opc));
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case Mips::FCOND_F:
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case Mips::FCOND_UN:
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case Mips::FCOND_OEQ:
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case Mips::FCOND_UEQ:
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case Mips::FCOND_OLT:
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case Mips::FCOND_ULT:
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case Mips::FCOND_OLE:
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case Mips::FCOND_ULE:
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case Mips::FCOND_SF:
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case Mips::FCOND_NGLE:
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case Mips::FCOND_SEQ:
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case Mips::FCOND_NGL:
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case Mips::FCOND_LT:
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case Mips::FCOND_NGE:
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case Mips::FCOND_LE:
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case Mips::FCOND_NGT: return Mips::BC1T;
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case Mips::FCOND_T:
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case Mips::FCOND_OR:
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case Mips::FCOND_UNE:
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case Mips::FCOND_ONE:
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case Mips::FCOND_UGE:
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case Mips::FCOND_OGE:
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case Mips::FCOND_UGT:
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case Mips::FCOND_OGT:
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case Mips::FCOND_ST:
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case Mips::FCOND_GLE:
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case Mips::FCOND_SNE:
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case Mips::FCOND_GL:
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case Mips::FCOND_NLT:
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case Mips::FCOND_GE:
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case Mips::FCOND_NLE:
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case Mips::FCOND_GT: return Mips::BC1F;
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}
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}
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/// GetOppositeBranchCondition - Return the inverse of the specified
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/// condition, e.g. turning COND_E to COND_NE.
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Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
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{
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switch (CC) {
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default: llvm_unreachable("Illegal condition code!");
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case Mips::COND_E : return Mips::COND_NE;
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case Mips::COND_NE : return Mips::COND_E;
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case Mips::COND_GZ : return Mips::COND_LEZ;
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case Mips::COND_GEZ : return Mips::COND_LZ;
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case Mips::COND_LZ : return Mips::COND_GEZ;
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case Mips::COND_LEZ : return Mips::COND_GZ;
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case Mips::FCOND_F : return Mips::FCOND_T;
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case Mips::FCOND_UN : return Mips::FCOND_OR;
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case Mips::FCOND_OEQ: return Mips::FCOND_UNE;
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case Mips::FCOND_UEQ: return Mips::FCOND_ONE;
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case Mips::FCOND_OLT: return Mips::FCOND_UGE;
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case Mips::FCOND_ULT: return Mips::FCOND_OGE;
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case Mips::FCOND_OLE: return Mips::FCOND_UGT;
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case Mips::FCOND_ULE: return Mips::FCOND_OGT;
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case Mips::FCOND_SF: return Mips::FCOND_ST;
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case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
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case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
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case Mips::FCOND_NGL: return Mips::FCOND_GL;
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case Mips::FCOND_LT: return Mips::FCOND_NLT;
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case Mips::FCOND_NGE: return Mips::FCOND_GE;
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case Mips::FCOND_LE: return Mips::FCOND_NLE;
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case Mips::FCOND_NGT: return Mips::FCOND_GT;
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}
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for (int i=0; i<NumOp-1; i++)
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Cond.push_back(Inst->getOperand(i));
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}
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bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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@ -323,91 +262,92 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const
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{
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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if (I == REnd || !isUnpredicatedTerminator(&*I)) {
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// If this block ends with no branches (it just falls through to its succ)
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// just return false, leaving TBB/FBB null.
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TBB = FBB = NULL;
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return false;
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}
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MachineInstr *LastInst = &*I;
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unsigned LastOpc = LastInst->getOpcode();
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// Not an analyzable branch (must be an indirect jump).
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if (!GetAnalyzableBrOpc(LastOpc))
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return true;
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// Get the second to last instruction in the block.
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unsigned SecondLastOpc = 0;
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MachineInstr *SecondLastInst = NULL;
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if (++I != REnd) {
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SecondLastInst = &*I;
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SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
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// Not an analyzable branch (must be an indirect jump).
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if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
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return true;
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}
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (!LastInst->getDesc().isBranch())
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return true;
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if (!SecondLastOpc) {
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// Unconditional branch
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if (LastOpc == Mips::J) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
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if (BranchCode == Mips::COND_INVALID)
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return true; // Can't handle indirect branch.
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// Conditional branch
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// Block ends with fall-through condbranch.
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if (LastOpc != Mips::COND_INVALID) {
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int LastNumOp = LastInst->getNumOperands();
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TBB = LastInst->getOperand(LastNumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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for (int i=0; i<LastNumOp-1; i++) {
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Cond.push_back(LastInst->getOperand(i));
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}
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return false;
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}
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AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
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return false;
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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// If we reached here, there are two branches.
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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if (++I != REnd && isUnpredicatedTerminator(&*I))
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return true;
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// If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
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// If second to last instruction is an unconditional branch,
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// analyze it and remove the last instruction.
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if (SecondLastOpc == Mips::J) {
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// Return if the last instruction cannot be removed.
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if (!AllowModify)
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return true;
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if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
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int SecondNumOp = SecondLastInst->getNumOperands();
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TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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for (int i=0; i<SecondNumOp-1; i++) {
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Cond.push_back(SecondLastInst->getOperand(i));
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}
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The last
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// one is not executed, so remove it.
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if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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LastInst->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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// Conditional branch followed by an unconditional branch.
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// The last one must be unconditional.
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if (LastOpc != Mips::J)
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return true;
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AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB, DebugLoc DL,
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const SmallVectorImpl<MachineOperand>& Cond)
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const {
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unsigned Opc = Cond[0].getImm();
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const TargetInstrDesc &TID = get(Opc);
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, TID);
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for (unsigned i = 1; i < Cond.size(); ++i)
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MIB.addReg(Cond[i].getReg());
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MIB.addMBB(TBB);
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}
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unsigned MipsInstrInfo::
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@ -417,72 +357,53 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
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"Mips branch conditions can have two|three components!");
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if (FBB == 0) { // One way branch.
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if (Cond.empty()) {
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// Unconditional branch?
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BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
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} else {
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// Conditional branch.
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unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
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const TargetInstrDesc &TID = get(Opc);
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if (TID.getNumOperands() == 3)
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BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
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.addReg(Cond[2].getReg())
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.addMBB(TBB);
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else
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BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
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.addMBB(TBB);
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}
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return 1;
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}
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// # of condition operands:
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// Unconditional branches: 0
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// Floating point branches: 1 (opc)
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// Int BranchZero: 2 (opc, reg)
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// Int Branch: 3 (opc, reg0, reg1)
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assert((Cond.size() <= 3) &&
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"# of Mips branch conditions must be <= 3!");
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// Two-way Conditional branch.
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unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
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const TargetInstrDesc &TID = get(Opc);
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if (FBB) {
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BuildCondBr(MBB, TBB, DL, Cond);
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BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
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return 2;
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}
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if (TID.getNumOperands() == 3)
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BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
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.addMBB(TBB);
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else
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BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
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return 2;
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// One way branch.
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// Unconditional branch.
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if (Cond.empty())
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BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
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else // Conditional branch.
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BuildCondBr(MBB, TBB, DL, Cond);
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return 1;
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}
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unsigned MipsInstrInfo::
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RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return 0;
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--I;
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}
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if (I->getOpcode() != Mips::J &&
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GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
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return 0;
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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MachineBasicBlock::reverse_iterator FirstBr;
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unsigned removed;
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// Remove the branch.
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I->eraseFromParent();
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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I = MBB.end();
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FirstBr = I;
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if (I == MBB.begin()) return 1;
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--I;
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if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
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return 1;
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// Up to 2 branches are removed.
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// Note that indirect branches are not removed.
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for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
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if (!GetAnalyzableBrOpc(I->getOpcode()))
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break;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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MBB.erase(I.base(), FirstBr.base());
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return removed;
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}
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/// ReverseBranchCondition - Return the inverse opcode of the
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@ -490,9 +411,9 @@ RemoveBranch(MachineBasicBlock &MBB) const
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bool MipsInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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{
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assert( (Cond.size() == 3 || Cond.size() == 2) &&
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assert( (Cond.size() && Cond.size() <= 3) &&
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"Invalid Mips branch condition!");
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Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
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Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
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return false;
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}
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@ -70,24 +70,12 @@ namespace Mips {
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FCOND_NLT,
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FCOND_GE,
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FCOND_NLE,
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FCOND_GT,
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// Only integer conditions
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COND_E,
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COND_GZ,
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COND_GEZ,
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COND_LZ,
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COND_LEZ,
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COND_NE,
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COND_INVALID
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FCOND_GT
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};
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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|
||||
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
|
||||
/// e.g. turning COND_E to COND_NE.
|
||||
CondCode GetOppositeBranchCondition(Mips::CondCode CC);
|
||||
/// GetOppositeBranchOpc - Return the inverse of the specified
|
||||
/// opcode, e.g. turning BEQ to BNE.
|
||||
unsigned GetOppositeBranchOpc(unsigned Opc);
|
||||
|
||||
/// MipsCCToString - Map each FP condition code to its string
|
||||
inline static const char *MipsFCCToString(Mips::CondCode CC)
|
||||
@ -196,6 +184,12 @@ public:
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool AllowModify) const;
|
||||
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
|
||||
private:
|
||||
void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
|
||||
const SmallVectorImpl<MachineOperand>& Cond) const;
|
||||
|
||||
public:
|
||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
|
||||
46
test/CodeGen/Mips/analyzebranch.ll
Normal file
46
test/CodeGen/Mips/analyzebranch.ll
Normal file
@ -0,0 +1,46 @@
|
||||
; RUN: llc -march=mips < %s | FileCheck %s
|
||||
|
||||
define double @foo(double %a, double %b) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: bc1f $BB0_2
|
||||
; CHECK: nop
|
||||
; CHECK: # BB#1:
|
||||
|
||||
%cmp = fcmp ogt double %a, 0.000000e+00
|
||||
br i1 %cmp, label %if.end6, label %if.else
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%cmp3 = fcmp ogt double %b, 0.000000e+00
|
||||
br i1 %cmp3, label %if.end6, label %return
|
||||
|
||||
if.end6: ; preds = %if.else, %entry
|
||||
%c.0 = phi double [ %a, %entry ], [ 0.000000e+00, %if.else ]
|
||||
%sub = fsub double %b, %c.0
|
||||
%mul = fmul double %sub, 2.000000e+00
|
||||
br label %return
|
||||
|
||||
return: ; preds = %if.else, %if.end6
|
||||
%retval.0 = phi double [ %mul, %if.end6 ], [ 0.000000e+00, %if.else ]
|
||||
ret double %retval.0
|
||||
}
|
||||
|
||||
define void @f1(float %f) nounwind {
|
||||
entry:
|
||||
; CHECK: bc1t $BB1_2
|
||||
; CHECK: nop
|
||||
; CHECK: # BB#1:
|
||||
%cmp = fcmp une float %f, 0.000000e+00
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @abort() noreturn
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
tail call void (...)* @f2() nounwind
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @abort() noreturn nounwind
|
||||
|
||||
declare void @f2(...)
|
||||
@ -10,9 +10,9 @@ entry:
|
||||
; CHECK-MIPS32R2: c.olt.s
|
||||
; CHECK-MIPS32R2: movt
|
||||
; CHECK-MIPS1: c.olt.s
|
||||
; CHECK-MIPS1: bc1f
|
||||
; CHECK-MIPS1: bc1t
|
||||
; CHECK-MIPS1: c.olt.s
|
||||
; CHECK-MIPS1: bc1f
|
||||
; CHECK-MIPS1: bc1t
|
||||
%cmp = fcmp olt float %f0, %f1
|
||||
%conv = zext i1 %cmp to i32
|
||||
%tmp2 = load i32* @g1, align 4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user