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AArch64/ARM64: port more AArch64 tests to ARM64.
llvm-svn: 206592
This commit is contained in:
Tim Northover
parent
56351e91d9
commit
c327e9b2cf
@ -1,5 +1,6 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -mattr=+crypto | FileCheck %s
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; RUN: not llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
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; arm64 has a separate test for this, covering the same features (crypto.ll). N.b. NO-CRYPTO will need porting.
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declare <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32>, <4 x i32>, <4 x i32>) #1
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <2 x float> @test_vfma_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) {
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; CHECK: test_vfma_lane_f32:
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@ -1,4 +1,5 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; arm64 has duplicates for this functionality in vcmp.ll.
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declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>)
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declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>)
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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define <2 x float> @fmla2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
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;CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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define <1 x double> @test_fpround_v1f128(<1 x fp128>* %a) {
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; CHECK-LABEL: test_fpround_v1f128:
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; arm64 has a duplicate for all these tests in vsqrt.ll
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; Set of tests for when the intrinsic is used.
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@ -1,4 +1,5 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; arm64 duplicates these in vhadd.ll and vhsub.ll
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declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8>, <8 x i8>)
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; arm64 does not use these pseudo-vectors, and they're not blessed by the PCS. Skipping.
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; Test load/store of v1i8, v1i16, v1i32 types can be selected correctly
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define void @load.store.v1i8(<1 x i8>* %ptr, <1 x i8>* %ptr2) {
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@ -1,4 +1,5 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; These duplicate arm64 tests in vmax.ll
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declare <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8>, <8 x i8>)
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@ -1,4 +1,5 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; These duplicate tests in arm64's vmax.ll
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declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>)
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@ -1,4 +1,5 @@
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;RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; arm64 already has copies of these tests (scattered).
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declare <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64>)
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@ -1,5 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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; arm64 has a separate copy of these in aarch64-neon-misc.ll due to different intrinsics.
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define <8 x i8> @test_vrev16_s8(<8 x i8> %a) #0 {
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; CHECK: rev16 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
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@ -1,218 +1,276 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
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define <8 x i8> @movi8b() {
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;CHECK: movi {{v[0-9]+}}.8b, #0x8
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; CHECK-LABEL: movi8b:
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; CHECK: movi {{v[0-9]+}}.8b, #{{0x8|8}}
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ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <16 x i8> @movi16b() {
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;CHECK: movi {{v[0-9]+}}.16b, #0x8
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; CHECK-LABEL: movi16b:
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; CHECK: movi {{v[0-9]+}}.16b, #{{0x8|8}}
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ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <2 x i32> @movi2s_lsl0() {
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;CHECK: movi {{v[0-9]+}}.2s, #0xff
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; CHECK-LABEL: movi2s_lsl0:
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; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff
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; CHECK-ARM64: movi {{d[0-9]+}}, #0x0000ff000000ff
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ret <2 x i32> < i32 255, i32 255 >
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}
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define <2 x i32> @movi2s_lsl8() {
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;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #8
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; CHECK-LABEL: movi2s_lsl8:
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; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, lsl #8
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; CHECK-ARM64: movi {{d[0-9]+}}, #0x00ff000000ff00
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ret <2 x i32> < i32 65280, i32 65280 >
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}
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define <2 x i32> @movi2s_lsl16() {
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;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #16
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; CHECK-LABEL: movi2s_lsl16:
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; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, lsl #16
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; CHECK-ARM64: movi {{d[0-9]+}}, #0xff000000ff0000
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ret <2 x i32> < i32 16711680, i32 16711680 >
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}
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define <2 x i32> @movi2s_lsl24() {
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;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #24
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; CHECK-LABEL: movi2s_lsl24:
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; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, lsl #24
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; CHECK-ARM64: movi {{d[0-9]+}}, #0xff000000ff000000
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ret <2 x i32> < i32 4278190080, i32 4278190080 >
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}
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define <4 x i32> @movi4s_lsl0() {
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;CHECK: movi {{v[0-9]+}}.4s, #0xff
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; CHECK-LABEL: movi4s_lsl0:
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; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff
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; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0x0000ff000000ff
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ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
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}
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define <4 x i32> @movi4s_lsl8() {
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;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #8
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; CHECK-LABEL: movi4s_lsl8:
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; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, lsl #8
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; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0x00ff000000ff00
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ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
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}
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define <4 x i32> @movi4s_lsl16() {
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;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #16
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; CHECK-LABEL: movi4s_lsl16:
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; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, lsl #16
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; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0xff000000ff0000
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ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
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}
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define <4 x i32> @movi4s_lsl24() {
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;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #24
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; CHECK-LABEL: movi4s_lsl24:
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; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, lsl #24
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; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0xff000000ff000000
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ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
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}
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define <4 x i16> @movi4h_lsl0() {
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;CHECK: movi {{v[0-9]+}}.4h, #0xff
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; CHECK-LABEL: movi4h_lsl0:
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; CHECK-AARCH64: movi {{v[0-9]+}}.4h, #0xff
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; CHECK-ARM64: movi {{d[0-9]+}}, #0xff00ff00ff00ff
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ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
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}
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define <4 x i16> @movi4h_lsl8() {
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;CHECK: movi {{v[0-9]+}}.4h, #0xff, lsl #8
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; CHECK-LABEL: movi4h_lsl8:
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; CHECK-AARCH64: movi {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
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; CHECK-ARM64: movi d0, #0xff00ff00ff00ff00
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ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
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}
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define <8 x i16> @movi8h_lsl0() {
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;CHECK: movi {{v[0-9]+}}.8h, #0xff
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; CHECK-LABEL: movi8h_lsl0:
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; CHECK-AARCH64: movi {{v[0-9]+}}.8h, #{{0xff|255}}
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; CHECK-ARM64: movi v0.2d, #0xff00ff00ff00ff
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ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
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}
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define <8 x i16> @movi8h_lsl8() {
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;CHECK: movi {{v[0-9]+}}.8h, #0xff, lsl #8
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; CHECK-LABEL: movi8h_lsl8:
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; CHECK-AARCH64: movi {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
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; CHECK-ARM64: movi v0.2d, #0xff00ff00ff00ff00
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ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
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}
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define <2 x i32> @mvni2s_lsl0() {
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;CHECK: mvni {{v[0-9]+}}.2s, #0x10
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; CHECK-LABEL: mvni2s_lsl0:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}
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ret <2 x i32> < i32 4294967279, i32 4294967279 >
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}
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define <2 x i32> @mvni2s_lsl8() {
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;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #8
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; CHECK-LABEL: mvni2s_lsl8:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8
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ret <2 x i32> < i32 4294963199, i32 4294963199 >
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}
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define <2 x i32> @mvni2s_lsl16() {
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;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #16
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; CHECK-LABEL: mvni2s_lsl16:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16
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ret <2 x i32> < i32 4293918719, i32 4293918719 >
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}
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define <2 x i32> @mvni2s_lsl24() {
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;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #24
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; CHECK-LABEL: mvni2s_lsl24:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24
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ret <2 x i32> < i32 4026531839, i32 4026531839 >
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}
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define <4 x i32> @mvni4s_lsl0() {
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;CHECK: mvni {{v[0-9]+}}.4s, #0x10
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; CHECK-LABEL: mvni4s_lsl0:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}
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ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
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}
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define <4 x i32> @mvni4s_lsl8() {
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;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #8
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; CHECK-LABEL: mvni4s_lsl8:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8
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ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
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}
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define <4 x i32> @mvni4s_lsl16() {
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;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #16
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; CHECK-LABEL: mvni4s_lsl16:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16
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ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
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}
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define <4 x i32> @mvni4s_lsl24() {
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;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #24
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; CHECK-LABEL: mvni4s_lsl24:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24
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ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
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}
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define <4 x i16> @mvni4h_lsl0() {
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;CHECK: mvni {{v[0-9]+}}.4h, #0x10
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; CHECK-LABEL: mvni4h_lsl0:
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; CHECK: mvni {{v[0-9]+}}.4h, #{{0x10|16}}
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ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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define <4 x i16> @mvni4h_lsl8() {
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;CHECK: mvni {{v[0-9]+}}.4h, #0x10, lsl #8
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; CHECK-LABEL: mvni4h_lsl8:
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; CHECK: mvni {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8
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ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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define <8 x i16> @mvni8h_lsl0() {
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;CHECK: mvni {{v[0-9]+}}.8h, #0x10
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; CHECK-LABEL: mvni8h_lsl0:
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; CHECK: mvni {{v[0-9]+}}.8h, #{{0x10|16}}
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ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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define <8 x i16> @mvni8h_lsl8() {
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;CHECK: mvni {{v[0-9]+}}.8h, #0x10, lsl #8
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; CHECK-LABEL: mvni8h_lsl8:
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; CHECK: mvni {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8
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ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
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;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #8
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; CHECK-LABEL: movi2s_msl8:
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; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, msl #8
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; CHECK-ARM64: movi {{d[0-9]+}}, #0x00ffff0000ffff
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ret <2 x i32> < i32 65535, i32 65535 >
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}
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define <2 x i32> @movi2s_msl16() {
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;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #16
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; CHECK-LABEL: movi2s_msl16:
|
||||
; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, msl #16
|
||||
; CHECK-ARM64: movi d0, #0xffffff00ffffff
|
||||
ret <2 x i32> < i32 16777215, i32 16777215 >
|
||||
}
|
||||
|
||||
|
||||
define <4 x i32> @movi4s_msl8() {
|
||||
;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #8
|
||||
; CHECK-LABEL: movi4s_msl8:
|
||||
; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, msl #8
|
||||
; CHECK-ARM64: movi v0.2d, #0x00ffff0000ffff
|
||||
ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
|
||||
}
|
||||
|
||||
define <4 x i32> @movi4s_msl16() {
|
||||
;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #16
|
||||
; CHECK-LABEL: movi4s_msl16:
|
||||
; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, msl #16
|
||||
; CHECK-ARM64: movi v0.2d, #0xffffff00ffffff
|
||||
ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
|
||||
}
|
||||
|
||||
define <2 x i32> @mvni2s_msl8() {
|
||||
;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #8
|
||||
; CHECK-LABEL: mvni2s_msl8:
|
||||
; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #8
|
||||
ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
|
||||
}
|
||||
|
||||
define <2 x i32> @mvni2s_msl16() {
|
||||
;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #16
|
||||
; CHECK-LABEL: mvni2s_msl16:
|
||||
; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #16
|
||||
ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
|
||||
}
|
||||
|
||||
define <4 x i32> @mvni4s_msl8() {
|
||||
;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #8
|
||||
; CHECK-LABEL: mvni4s_msl8:
|
||||
; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #8
|
||||
ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
|
||||
}
|
||||
|
||||
define <4 x i32> @mvni4s_msl16() {
|
||||
;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #16
|
||||
; CHECK-LABEL: mvni4s_msl16:
|
||||
; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #16
|
||||
ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
|
||||
}
|
||||
|
||||
define <2 x i64> @movi2d() {
|
||||
;CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
|
||||
; CHECK-LABEL: movi2d:
|
||||
; CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
|
||||
ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
|
||||
}
|
||||
|
||||
define <1 x i64> @movid() {
|
||||
;CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
|
||||
; CHECK-LABEL: movid:
|
||||
; CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
|
||||
ret <1 x i64> < i64 18374687574888349695 >
|
||||
}
|
||||
|
||||
define <2 x float> @fmov2s() {
|
||||
;CHECK: fmov {{v[0-9]+}}.2s, #-12.00000000
|
||||
; CHECK-LABEL: fmov2s:
|
||||
; CHECK: fmov {{v[0-9]+}}.2s, #{{-12.00000000|-1.200000e\+01}}
|
||||
ret <2 x float> < float -1.2e1, float -1.2e1>
|
||||
}
|
||||
|
||||
define <4 x float> @fmov4s() {
|
||||
;CHECK: fmov {{v[0-9]+}}.4s, #-12.00000000
|
||||
; CHECK-LABEL: fmov4s:
|
||||
; CHECK: fmov {{v[0-9]+}}.4s, #{{-12.00000000|-1.200000e\+01}}
|
||||
ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
|
||||
}
|
||||
|
||||
define <2 x double> @fmov2d() {
|
||||
;CHECK: fmov {{v[0-9]+}}.2d, #-12.00000000
|
||||
; CHECK-LABEL: fmov2d:
|
||||
; CHECK: fmov {{v[0-9]+}}.2d, #{{-12.00000000|-1.200000e\+01}}
|
||||
ret <2 x double> < double -1.2e1, double -1.2e1>
|
||||
}
|
||||
|
||||
define <2 x i32> @movi1d_1() {
|
||||
; CHECK: movi d0, #0xffffffff0000
|
||||
; CHECK-LABEL: movi1d_1:
|
||||
; CHECK: movi d0, #0x{{0*}}ffffffff0000
|
||||
ret <2 x i32> < i32 -65536, i32 65535>
|
||||
}
|
||||
|
||||
|
||||
declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
|
||||
define <2 x i32> @movi1d() {
|
||||
; CHECK-LABEL: movi1d:
|
||||
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
|
||||
; CHECK-NEXT: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
|
||||
; CHECK-NEXT: movi d1, #0xffffffff0000
|
||||
; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
|
||||
; CHECK-NEXT: movi d1, #0x{{0*}}ffffffff0000
|
||||
%1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
|
||||
ret <2 x i32> %1
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
|
||||
|
||||
; arm64 has its own copy of this because of the intrinsics
|
||||
|
||||
define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {
|
||||
;CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
|
||||
|
||||
; Check that the DAGCombiner does not crash with an assertion failure
|
||||
; when performing a target specific combine to simplify a 'or' dag node
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,5 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
; Just intrinsic calls: arm64 has similar in vhadd.ll
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8>, <8 x i8>)
|
||||
declare <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8>, <8 x i8>)
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
; Just intrinsic calls: arm64 has similar in vshift.ll
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>)
|
||||
declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
|
||||
; Just intrinsic calls: arm64 has similar in vqadd.ll
|
||||
declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>)
|
||||
declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>)
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
; Just intrinsic calls: arm64 has similar in vshift.ll
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8>, <8 x i8>)
|
||||
declare <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8>, <8 x i8>)
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
; Just intrinsic calls: arm64 has similar in vshift.ll
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>)
|
||||
declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
797
test/CodeGen/ARM64/aarch64-neon-mul-div.ll
Normal file
797
test/CodeGen/ARM64/aarch64-neon-mul-div.ll
Normal file
@ -0,0 +1,797 @@
|
||||
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
|
||||
; arm64 has its own copy of this because of the intrinsics
|
||||
|
||||
define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {
|
||||
; CHECK-LABEL: mul8xi8:
|
||||
; CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = mul <8 x i8> %A, %B;
|
||||
ret <8 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <16 x i8> @mul16xi8(<16 x i8> %A, <16 x i8> %B) {
|
||||
; CHECK-LABEL: mul16xi8:
|
||||
; CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = mul <16 x i8> %A, %B;
|
||||
ret <16 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i16> @mul4xi16(<4 x i16> %A, <4 x i16> %B) {
|
||||
; CHECK-LABEL: mul4xi16:
|
||||
; CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
|
||||
%tmp3 = mul <4 x i16> %A, %B;
|
||||
ret <4 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i16> @mul8xi16(<8 x i16> %A, <8 x i16> %B) {
|
||||
; CHECK-LABEL: mul8xi16:
|
||||
; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
|
||||
%tmp3 = mul <8 x i16> %A, %B;
|
||||
ret <8 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i32> @mul2xi32(<2 x i32> %A, <2 x i32> %B) {
|
||||
; CHECK-LABEL: mul2xi32:
|
||||
; CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
|
||||
%tmp3 = mul <2 x i32> %A, %B;
|
||||
ret <2 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
|
||||
; CHECK-LABEL: mul4x32:
|
||||
; CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
%tmp3 = mul <4 x i32> %A, %B;
|
||||
ret <4 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i64> @mul1xi64(<1 x i64> %A, <1 x i64> %B) {
|
||||
; CHECK-LABEL: mul1xi64:
|
||||
; CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
|
||||
%tmp3 = mul <1 x i64> %A, %B;
|
||||
ret <1 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) {
|
||||
; CHECK-LABEL: mul2xi64:
|
||||
; CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
|
||||
; CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
|
||||
%tmp3 = mul <2 x i64> %A, %B;
|
||||
ret <2 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
; CHECK-LABEL: mul2xfloat:
|
||||
; CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
|
||||
%tmp3 = fmul <2 x float> %A, %B;
|
||||
ret <2 x float> %tmp3
|
||||
}
|
||||
|
||||
define <4 x float> @mul4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
; CHECK-LABEL: mul4xfloat:
|
||||
; CHECK: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
%tmp3 = fmul <4 x float> %A, %B;
|
||||
ret <4 x float> %tmp3
|
||||
}
|
||||
define <2 x double> @mul2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
; CHECK-LABEL: mul2xdouble:
|
||||
; CHECK: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
||||
%tmp3 = fmul <2 x double> %A, %B;
|
||||
ret <2 x double> %tmp3
|
||||
}
|
||||
|
||||
|
||||
define <2 x float> @div2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
; CHECK-LABEL: div2xfloat:
|
||||
; CHECK: fdiv {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
|
||||
%tmp3 = fdiv <2 x float> %A, %B;
|
||||
ret <2 x float> %tmp3
|
||||
}
|
||||
|
||||
define <4 x float> @div4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
; CHECK-LABEL: div4xfloat:
|
||||
; CHECK: fdiv {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
%tmp3 = fdiv <4 x float> %A, %B;
|
||||
ret <4 x float> %tmp3
|
||||
}
|
||||
define <2 x double> @div2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
; CHECK-LABEL: div2xdouble:
|
||||
; CHECK: fdiv {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
||||
%tmp3 = fdiv <2 x double> %A, %B;
|
||||
ret <2 x double> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i8> @sdiv1x8(<1 x i8> %A, <1 x i8> %B) {
|
||||
; CHECK-LABEL: sdiv1x8:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <1 x i8> %A, %B;
|
||||
ret <1 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i8> @sdiv8x8(<8 x i8> %A, <8 x i8> %B) {
|
||||
; CHECK-LABEL: sdiv8x8:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <8 x i8> %A, %B;
|
||||
ret <8 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <16 x i8> @sdiv16x8(<16 x i8> %A, <16 x i8> %B) {
|
||||
; CHECK-LABEL: sdiv16x8:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <16 x i8> %A, %B;
|
||||
ret <16 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i16> @sdiv1x16(<1 x i16> %A, <1 x i16> %B) {
|
||||
; CHECK-LABEL: sdiv1x16:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <1 x i16> %A, %B;
|
||||
ret <1 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i16> @sdiv4x16(<4 x i16> %A, <4 x i16> %B) {
|
||||
; CHECK-LABEL: sdiv4x16:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <4 x i16> %A, %B;
|
||||
ret <4 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i16> @sdiv8x16(<8 x i16> %A, <8 x i16> %B) {
|
||||
; CHECK-LABEL: sdiv8x16:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <8 x i16> %A, %B;
|
||||
ret <8 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i32> @sdiv1x32(<1 x i32> %A, <1 x i32> %B) {
|
||||
; CHECK-LABEL: sdiv1x32:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <1 x i32> %A, %B;
|
||||
ret <1 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i32> @sdiv2x32(<2 x i32> %A, <2 x i32> %B) {
|
||||
; CHECK-LABEL: sdiv2x32:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <2 x i32> %A, %B;
|
||||
ret <2 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i32> @sdiv4x32(<4 x i32> %A, <4 x i32> %B) {
|
||||
; CHECK-LABEL: sdiv4x32:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = sdiv <4 x i32> %A, %B;
|
||||
ret <4 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i64> @sdiv1x64(<1 x i64> %A, <1 x i64> %B) {
|
||||
; CHECK-LABEL: sdiv1x64:
|
||||
; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = sdiv <1 x i64> %A, %B;
|
||||
ret <1 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i64> @sdiv2x64(<2 x i64> %A, <2 x i64> %B) {
|
||||
; CHECK-LABEL: sdiv2x64:
|
||||
; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = sdiv <2 x i64> %A, %B;
|
||||
ret <2 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i8> @udiv1x8(<1 x i8> %A, <1 x i8> %B) {
|
||||
; CHECK-LABEL: udiv1x8:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <1 x i8> %A, %B;
|
||||
ret <1 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i8> @udiv8x8(<8 x i8> %A, <8 x i8> %B) {
|
||||
; CHECK-LABEL: udiv8x8:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <8 x i8> %A, %B;
|
||||
ret <8 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <16 x i8> @udiv16x8(<16 x i8> %A, <16 x i8> %B) {
|
||||
; CHECK-LABEL: udiv16x8:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <16 x i8> %A, %B;
|
||||
ret <16 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i16> @udiv1x16(<1 x i16> %A, <1 x i16> %B) {
|
||||
; CHECK-LABEL: udiv1x16:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <1 x i16> %A, %B;
|
||||
ret <1 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i16> @udiv4x16(<4 x i16> %A, <4 x i16> %B) {
|
||||
; CHECK-LABEL: udiv4x16:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <4 x i16> %A, %B;
|
||||
ret <4 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i16> @udiv8x16(<8 x i16> %A, <8 x i16> %B) {
|
||||
; CHECK-LABEL: udiv8x16:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <8 x i16> %A, %B;
|
||||
ret <8 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i32> @udiv1x32(<1 x i32> %A, <1 x i32> %B) {
|
||||
; CHECK-LABEL: udiv1x32:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <1 x i32> %A, %B;
|
||||
ret <1 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i32> @udiv2x32(<2 x i32> %A, <2 x i32> %B) {
|
||||
; CHECK-LABEL: udiv2x32:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <2 x i32> %A, %B;
|
||||
ret <2 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i32> @udiv4x32(<4 x i32> %A, <4 x i32> %B) {
|
||||
; CHECK-LABEL: udiv4x32:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = udiv <4 x i32> %A, %B;
|
||||
ret <4 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i64> @udiv1x64(<1 x i64> %A, <1 x i64> %B) {
|
||||
; CHECK-LABEL: udiv1x64:
|
||||
; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = udiv <1 x i64> %A, %B;
|
||||
ret <1 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i64> @udiv2x64(<2 x i64> %A, <2 x i64> %B) {
|
||||
; CHECK-LABEL: udiv2x64:
|
||||
; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = udiv <2 x i64> %A, %B;
|
||||
ret <2 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i8> @srem1x8(<1 x i8> %A, <1 x i8> %B) {
|
||||
; CHECK-LABEL: srem1x8:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <1 x i8> %A, %B;
|
||||
ret <1 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i8> @srem8x8(<8 x i8> %A, <8 x i8> %B) {
|
||||
; CHECK-LABEL: srem8x8:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <8 x i8> %A, %B;
|
||||
ret <8 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <16 x i8> @srem16x8(<16 x i8> %A, <16 x i8> %B) {
|
||||
; CHECK-LABEL: srem16x8:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <16 x i8> %A, %B;
|
||||
ret <16 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i16> @srem1x16(<1 x i16> %A, <1 x i16> %B) {
|
||||
; CHECK-LABEL: srem1x16:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <1 x i16> %A, %B;
|
||||
ret <1 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i16> @srem4x16(<4 x i16> %A, <4 x i16> %B) {
|
||||
; CHECK-LABEL: srem4x16:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <4 x i16> %A, %B;
|
||||
ret <4 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i16> @srem8x16(<8 x i16> %A, <8 x i16> %B) {
|
||||
; CHECK-LABEL: srem8x16:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <8 x i16> %A, %B;
|
||||
ret <8 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i32> @srem1x32(<1 x i32> %A, <1 x i32> %B) {
|
||||
; CHECK-LABEL: srem1x32:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <1 x i32> %A, %B;
|
||||
ret <1 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i32> @srem2x32(<2 x i32> %A, <2 x i32> %B) {
|
||||
; CHECK-LABEL: srem2x32:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <2 x i32> %A, %B;
|
||||
ret <2 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i32> @srem4x32(<4 x i32> %A, <4 x i32> %B) {
|
||||
; CHECK-LABEL: srem4x32:
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = srem <4 x i32> %A, %B;
|
||||
ret <4 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i64> @srem1x64(<1 x i64> %A, <1 x i64> %B) {
|
||||
; CHECK-LABEL: srem1x64:
|
||||
; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = srem <1 x i64> %A, %B;
|
||||
ret <1 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i64> @srem2x64(<2 x i64> %A, <2 x i64> %B) {
|
||||
; CHECK-LABEL: srem2x64:
|
||||
; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = srem <2 x i64> %A, %B;
|
||||
ret <2 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i8> @urem1x8(<1 x i8> %A, <1 x i8> %B) {
|
||||
; CHECK-LABEL: urem1x8:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <1 x i8> %A, %B;
|
||||
ret <1 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i8> @urem8x8(<8 x i8> %A, <8 x i8> %B) {
|
||||
; CHECK-LABEL: urem8x8:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <8 x i8> %A, %B;
|
||||
ret <8 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <16 x i8> @urem16x8(<16 x i8> %A, <16 x i8> %B) {
|
||||
; CHECK-LABEL: urem16x8:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <16 x i8> %A, %B;
|
||||
ret <16 x i8> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i16> @urem1x16(<1 x i16> %A, <1 x i16> %B) {
|
||||
; CHECK-LABEL: urem1x16:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <1 x i16> %A, %B;
|
||||
ret <1 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i16> @urem4x16(<4 x i16> %A, <4 x i16> %B) {
|
||||
; CHECK-LABEL: urem4x16:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <4 x i16> %A, %B;
|
||||
ret <4 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <8 x i16> @urem8x16(<8 x i16> %A, <8 x i16> %B) {
|
||||
; CHECK-LABEL: urem8x16:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <8 x i16> %A, %B;
|
||||
ret <8 x i16> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i32> @urem1x32(<1 x i32> %A, <1 x i32> %B) {
|
||||
; CHECK-LABEL: urem1x32:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <1 x i32> %A, %B;
|
||||
ret <1 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i32> @urem2x32(<2 x i32> %A, <2 x i32> %B) {
|
||||
; CHECK-LABEL: urem2x32:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <2 x i32> %A, %B;
|
||||
ret <2 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <4 x i32> @urem4x32(<4 x i32> %A, <4 x i32> %B) {
|
||||
; CHECK-LABEL: urem4x32:
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
%tmp3 = urem <4 x i32> %A, %B;
|
||||
ret <4 x i32> %tmp3
|
||||
}
|
||||
|
||||
define <1 x i64> @urem1x64(<1 x i64> %A, <1 x i64> %B) {
|
||||
; CHECK-LABEL: urem1x64:
|
||||
; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = urem <1 x i64> %A, %B;
|
||||
ret <1 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <2 x i64> @urem2x64(<2 x i64> %A, <2 x i64> %B) {
|
||||
; CHECK-LABEL: urem2x64:
|
||||
; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
%tmp3 = urem <2 x i64> %A, %B;
|
||||
ret <2 x i64> %tmp3
|
||||
}
|
||||
|
||||
define <2 x float> @frem2f32(<2 x float> %A, <2 x float> %B) {
|
||||
; CHECK-LABEL: frem2f32:
|
||||
; CHECK: bl fmodf
|
||||
; CHECK: bl fmodf
|
||||
%tmp3 = frem <2 x float> %A, %B;
|
||||
ret <2 x float> %tmp3
|
||||
}
|
||||
|
||||
define <4 x float> @frem4f32(<4 x float> %A, <4 x float> %B) {
|
||||
; CHECK-LABEL: frem4f32:
|
||||
; CHECK: bl fmodf
|
||||
; CHECK: bl fmodf
|
||||
; CHECK: bl fmodf
|
||||
; CHECK: bl fmodf
|
||||
%tmp3 = frem <4 x float> %A, %B;
|
||||
ret <4 x float> %tmp3
|
||||
}
|
||||
|
||||
define <1 x double> @frem1d64(<1 x double> %A, <1 x double> %B) {
|
||||
; CHECK-LABEL: frem1d64:
|
||||
; CHECK: bl fmod
|
||||
%tmp3 = frem <1 x double> %A, %B;
|
||||
ret <1 x double> %tmp3
|
||||
}
|
||||
|
||||
define <2 x double> @frem2d64(<2 x double> %A, <2 x double> %B) {
|
||||
; CHECK-LABEL: frem2d64:
|
||||
; CHECK: bl fmod
|
||||
; CHECK: bl fmod
|
||||
%tmp3 = frem <2 x double> %A, %B;
|
||||
ret <2 x double> %tmp3
|
||||
}
|
||||
|
||||
declare <8 x i8> @llvm.arm64.neon.pmul.v8i8(<8 x i8>, <8 x i8>)
|
||||
declare <16 x i8> @llvm.arm64.neon.pmul.v16i8(<16 x i8>, <16 x i8>)
|
||||
|
||||
define <8 x i8> @poly_mulv8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
|
||||
; CHECK-LABEL: poly_mulv8i8:
|
||||
%prod = call <8 x i8> @llvm.arm64.neon.pmul.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
|
||||
; CHECK: pmul v0.8b, v0.8b, v1.8b
|
||||
ret <8 x i8> %prod
|
||||
}
|
||||
|
||||
define <16 x i8> @poly_mulv16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
|
||||
; CHECK-LABEL: poly_mulv16i8:
|
||||
%prod = call <16 x i8> @llvm.arm64.neon.pmul.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
|
||||
; CHECK: pmul v0.16b, v0.16b, v1.16b
|
||||
ret <16 x i8> %prod
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>)
|
||||
declare <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>)
|
||||
declare <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)
|
||||
declare <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)
|
||||
|
||||
define <4 x i16> @test_sqdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
|
||||
; CHECK-LABEL: test_sqdmulh_v4i16:
|
||||
%prod = call <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
|
||||
; CHECK: sqdmulh v0.4h, v0.4h, v1.4h
|
||||
ret <4 x i16> %prod
|
||||
}
|
||||
|
||||
define <8 x i16> @test_sqdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
|
||||
; CHECK-LABEL: test_sqdmulh_v8i16:
|
||||
%prod = call <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
|
||||
; CHECK: sqdmulh v0.8h, v0.8h, v1.8h
|
||||
ret <8 x i16> %prod
|
||||
}
|
||||
|
||||
define <2 x i32> @test_sqdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
|
||||
; CHECK-LABEL: test_sqdmulh_v2i32:
|
||||
%prod = call <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
|
||||
; CHECK: sqdmulh v0.2s, v0.2s, v1.2s
|
||||
ret <2 x i32> %prod
|
||||
}
|
||||
|
||||
define <4 x i32> @test_sqdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
|
||||
; CHECK-LABEL: test_sqdmulh_v4i32:
|
||||
%prod = call <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
|
||||
; CHECK: sqdmulh v0.4s, v0.4s, v1.4s
|
||||
ret <4 x i32> %prod
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
|
||||
declare <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
|
||||
declare <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
|
||||
declare <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
|
||||
|
||||
define <4 x i16> @test_sqrdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
|
||||
; CHECK-LABEL: test_sqrdmulh_v4i16:
|
||||
%prod = call <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
|
||||
; CHECK: sqrdmulh v0.4h, v0.4h, v1.4h
|
||||
ret <4 x i16> %prod
|
||||
}
|
||||
|
||||
define <8 x i16> @test_sqrdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
|
||||
; CHECK-LABEL: test_sqrdmulh_v8i16:
|
||||
%prod = call <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
|
||||
; CHECK: sqrdmulh v0.8h, v0.8h, v1.8h
|
||||
ret <8 x i16> %prod
|
||||
}
|
||||
|
||||
define <2 x i32> @test_sqrdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
|
||||
; CHECK-LABEL: test_sqrdmulh_v2i32:
|
||||
%prod = call <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
|
||||
; CHECK: sqrdmulh v0.2s, v0.2s, v1.2s
|
||||
ret <2 x i32> %prod
|
||||
}
|
||||
|
||||
define <4 x i32> @test_sqrdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
|
||||
; CHECK-LABEL: test_sqrdmulh_v4i32:
|
||||
%prod = call <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
|
||||
; CHECK: sqrdmulh v0.4s, v0.4s, v1.4s
|
||||
ret <4 x i32> %prod
|
||||
}
|
||||
|
||||
declare <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float>, <2 x float>)
|
||||
declare <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float>, <4 x float>)
|
||||
declare <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double>, <2 x double>)
|
||||
|
||||
define <2 x float> @fmulx_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
|
||||
; CHECK-LABEL: fmulx_v2f32:
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: fmulx v0.2s, v0.2s, v1.2s
|
||||
%val = call <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float> %lhs, <2 x float> %rhs)
|
||||
ret <2 x float> %val
|
||||
}
|
||||
|
||||
define <4 x float> @fmulx_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
|
||||
; CHECK-LABEL: fmulx_v4f32:
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: fmulx v0.4s, v0.4s, v1.4s
|
||||
%val = call <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float> %lhs, <4 x float> %rhs)
|
||||
ret <4 x float> %val
|
||||
}
|
||||
|
||||
define <2 x double> @fmulx_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
|
||||
; CHECK-LABEL: fmulx_v2f64:
|
||||
; Using registers other than v0, v1 and v2 are possible, but would be odd.
|
||||
; CHECK: fmulx v0.2d, v0.2d, v1.2d
|
||||
%val = call <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double> %lhs, <2 x double> %rhs)
|
||||
ret <2 x double> %val
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user