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[X86][AVX512] Tag VFPCLASS instructions scheduler class
llvm-svn: 319554
This commit is contained in:
Simon Pilgrim
parent
2ebb6656a6
commit
c36e35f115
@ -2363,34 +2363,39 @@ let Predicates = [HasAVX512] in {
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//handle fpclass instruction mask = op(reg_scalar,imm)
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// op(mem_scalar,imm)
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multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, Predicate prd> {
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OpndItins itins, X86VectorVTInfo _,
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Predicate prd> {
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let Predicates = [prd], ExeDomain = _.ExeDomain in {
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def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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(ins _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2)))], NoItinerary>;
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(i32 imm:$src2)))], itins.rr>,
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Sched<[itins.Sched]>;
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def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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(i32 imm:$src2))))], itins.rr>,
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EVEX_K, Sched<[itins.Sched]>;
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def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.IntScalarMemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,
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(OpNode _.ScalarIntMemCPat:$src1,
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(i32 imm:$src2)))], NoItinerary>;
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(i32 imm:$src2)))], itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.IntScalarMemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode _.ScalarIntMemCPat:$src1,
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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(i32 imm:$src2))))], itins.rm>,
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EVEX_K, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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@ -2398,34 +2403,39 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// fpclass(reg_vec, mem_vec, imm)
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// fpclass(reg_vec, broadcast(eltVt), imm)
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multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, string mem, string broadcast>{
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OpndItins itins, X86VectorVTInfo _,
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string mem, string broadcast>{
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let ExeDomain = _.ExeDomain in {
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def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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(ins _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2)))], NoItinerary>;
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(i32 imm:$src2)))], itins.rr>,
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Sched<[itins.Sched]>;
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def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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(i32 imm:$src2))))], itins.rr>,
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EVEX_K, Sched<[itins.Sched]>;
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def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##mem#
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,(OpNode
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(_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2)))], NoItinerary>;
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(i32 imm:$src2)))], itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##mem#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
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(_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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(i32 imm:$src2))))], itins.rm>,
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EVEX_K, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.ScalarMemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
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@ -2434,7 +2444,8 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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[(set _.KRC:$dst,(OpNode
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src1))),
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(i32 imm:$src2)))], NoItinerary>,EVEX_B;
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(i32 imm:$src2)))], itins.rm>,
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EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
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@ -2443,36 +2454,42 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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[(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src1))),
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(i32 imm:$src2))))], NoItinerary>,
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EVEX_B, EVEX_K;
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(i32 imm:$src2))))], itins.rm>,
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EVEX_B, EVEX_K, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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multiclass avx512_vector_fpclass_all<string OpcodeStr,
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AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
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string broadcast>{
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multiclass avx512_vector_fpclass_all<string OpcodeStr, AVX512VLVectorVTInfo _,
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bits<8> opc, SDNode OpNode,
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OpndItins itins, Predicate prd,
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string broadcast>{
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let Predicates = [prd] in {
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defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
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broadcast>, EVEX_V512;
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defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, itins,
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_.info512, "{z}", broadcast>, EVEX_V512;
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}
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let Predicates = [prd, HasVLX] in {
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defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
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broadcast>, EVEX_V128;
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defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
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broadcast>, EVEX_V256;
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defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, itins,
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_.info128, "{x}", broadcast>, EVEX_V128;
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defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, itins,
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_.info256, "{y}", broadcast>, EVEX_V256;
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}
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}
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// FIXME: Is there a better scheduler itinerary for VFPCLASS?
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multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
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bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
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defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
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VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
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VecOpNode, SSE_ALU_F32P, prd, "{l}">,
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EVEX_CD8<32, CD8VF>;
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defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
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VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
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VecOpNode, SSE_ALU_F64P, prd, "{q}">,
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EVEX_CD8<64, CD8VF> , VEX_W;
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defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
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f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
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SSE_ALU_F32S, f32x_info, prd>,
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EVEX_CD8<32, CD8VT1>;
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defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
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f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
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SSE_ALU_F64S, f64x_info, prd>,
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EVEX_CD8<64, CD8VT1>, VEX_W;
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}
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defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
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