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[mips][microMIPS] Implement BEQZC and BNEZC instructions

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Differential Revision: http://reviews.llvm.org/D15417

llvm-svn: 269755
This commit is contained in:
Zoran Jovanovic 2016-05-17 11:10:15 +00:00
parent a99b8023bb
commit c3850b81b8
8 changed files with 81 additions and 3 deletions
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15
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -209,6 +209,11 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
unsigned Offset,
uint64_t Address,
@ -1861,6 +1866,16 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<21>(Offset) << 1;
Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
unsigned Offset,
uint64_t Address,

20
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -343,6 +343,26 @@ getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
return 0;
}
/// getBranchTarget21OpValueMM - Return binary encoding of the branch
/// target operand for microMIPS. If the machine operand requires
/// relocation, record the relocation and return zero.
unsigned MipsMCCodeEmitter::
getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 2.
if (MO.isImm()) return MO.getImm() >> 1;
assert(MO.isExpr() &&
"getBranchTarget21OpValueMM expects only expressions or immediates");
// TODO: Push fixup.
return 0;
}
/// getBranchTarget26OpValue - Return binary encoding of the branch
/// target operand. If the machine operand requires relocation,
/// record the relocation and return zero.

7
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
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@ -137,6 +137,13 @@ public:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchTarget21OpValueMM - Return binary encoding of the branch
// offset operand for microMIPS. If the machine operand requires
// relocation,record the relocation and return zero.
unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchTarget26OpValue - Return binary encoding of the branch
// offset operand. If the machine operand requires relocation,
// record the relocation and return zero.

11
lib/Target/Mips/MicroMips32r6InstrFormats.td
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@ -993,3 +993,14 @@ class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst {
let Inst{15-12} = funct;
let Inst{11-0} = offset;
}
class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
bits<5> rs;
bits<21> offset;
bits<32> Inst;
let Inst{31-26} = funct;
let Inst{25-21} = rs;
let Inst{20-0} = offset;
}

20
lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -11,6 +11,13 @@
//
//===----------------------------------------------------------------------===//
def brtarget21_mm : Operand<OtherVT> {
let EncoderMethod = "getBranchTarget21OpValueMM";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget21MM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def brtarget26_mm : Operand<OtherVT> {
let EncoderMethod = "getBranchTarget26OpValueMM";
let OperandType = "OPERAND_PCREL";
@ -40,6 +47,8 @@ class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111001>;
class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
DecodeDisambiguates<"BlezGroupBranchMMR6">;
@ -1149,6 +1158,13 @@ class DVPEVP_MMR6_DESC_BASE<string opstr> {
class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">;
class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">;
class BEQZC_MMR6_DESC
: CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
MMR6Arch<"beqzc">;
class BNEZC_MMR6_DESC
: CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
MMR6Arch<"bnezc">;
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@ -1171,8 +1187,12 @@ def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
ISA_MICROMIPS32R6;
def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
ISA_MICROMIPS32R6;
def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
ISA_MICROMIPS32R6;
def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
ISA_MICROMIPS32R6;
def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,

7
lib/Target/Mips/Mips32r6InstrInfo.td
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@ -327,7 +327,8 @@ class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
}
class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
RegisterOperand GPROpnd>
: BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
@ -721,7 +722,7 @@ def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
@ -737,7 +738,7 @@ def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;

2
test/MC/Disassembler/Mips/micromips32r6/valid.txt
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@ -51,6 +51,8 @@
0xe0 0x40 0x02 0x9a # CHECK: bgtzalc $2, 1332
0xe0 0x42 0x02 0x9a # CHECK: bltzalc $2, 1332
0xc0 0x40 0x02 0x9a # CHECK: blezalc $2, 1332
0x80 0x60 0x00 0x20 # CHECK: beqzc $3, 64
0xa0 0x60 0x00 0x20 # CHECK: bnezc $3, 64
0xb4 0x37 0x96 0xb8 # CHECK: balc 7286128
0x94 0x37 0x96 0xb8 # CHECK: bc 7286128
0x00 0x44 0x0b 0x3c # CHECK: bitswap $4, $2

2
test/MC/Mips/micromips32r6/valid.s
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@ -32,6 +32,8 @@
bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0xe0,0x40,0x02,0x9a]
bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0xe0,0x42,0x02,0x9a]
blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0xc0,0x40,0x02,0x9a]
beqzc $3, 64 # CHECK: beqzc $3, 64 # encoding: [0x80,0x60,0x00,0x20]
bnezc $3, 64 # CHECK: bnezc $3, 64 # encoding: [0xa0,0x60,0x00,0x20]
balc 7286128 # CHECK: balc 7286128 # encoding: [0xb4,0x37,0x96,0xb8]
b 132 # CHECK: bc16 132 # encoding: [0xcc,0x42]
bc 7286128 # CHECK: bc 7286128 # encoding: [0x94,0x37,0x96,0xb8]