RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 02:33:06 +01:00
Code Issues Projects Releases Wiki Activity

[VPlan] Add plain text (not DOT's digraph) dumps

Browse Source 
I foresee two uses for this:
1) It's easier to use those in debugger.
2) Once we start implementing more VPlan-to-VPlan transformations (especially
   inner loop massaging stuff), using the vectorized LLVM IR as CHECK targets in
   LIT test would become too obscure. I can imagine that we'd want to CHECK
   against VPlan dumps after multiple transformations instead. That would be
   easier with plain text dumps than with DOT format.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D96628
This commit is contained in:
Andrei Elovikov 2021-03-18 11:32:34 -07:00
parent 041f7386ea
commit c3beafcfc6
9 changed files with 328 additions and 161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Transforms/Vectorize/LoopVectorizationPlanner.h
View File

@ -256,10 +256,7 @@ public:
/// best selected VPlan.
void executePlan(InnerLoopVectorizer &LB, DominatorTree *DT);
void printPlans(raw_ostream &O) {
for (const auto &Plan : VPlans)
O << *Plan;
}
void printPlans(raw_ostream &O);
/// Look through the existing plans and return true if we have one with all
/// the vectorization factors in question.

16
lib/Transforms/Vectorize/LoopVectorize.cpp
View File

@ -360,6 +360,10 @@ cl::opt<bool> llvm::EnableLoopVectorization(
"vectorize-loops", cl::init(true), cl::Hidden,
cl::desc("Run the Loop vectorization passes"));
cl::opt<bool> PrintVPlansInDotFormat(
"vplan-print-in-dot-format", cl::init(false), cl::Hidden,
cl::desc("Use dot format instead of plain text when dumping VPlans"));
/// A helper function that returns the type of loaded or stored value.
static Type *getMemInstValueType(Value *I) {
assert((isa<LoadInst>(I) || isa<StoreInst>(I)) &&
@ -7809,6 +7813,14 @@ void LoopVectorizationPlanner::executePlan(InnerLoopVectorizer &ILV,
ILV.printDebugTracesAtEnd();
}
void LoopVectorizationPlanner::printPlans(raw_ostream &O) {
for (const auto &Plan : VPlans)
if (PrintVPlansInDotFormat)
Plan->printDOT(O);
else
Plan->print(O);
}
void LoopVectorizationPlanner::collectTriviallyDeadInstructions(
SmallPtrSetImpl<Instruction *> &DeadInstructions) {
@ -9007,7 +9019,7 @@ void LoopVectorizationPlanner::adjustRecipesForInLoopReductions(
void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const {
O << Indent << "\"INTERLEAVE-GROUP with factor " << IG->getFactor() << " at ";
O << Indent << "INTERLEAVE-GROUP with factor " << IG->getFactor() << " at ";
IG->getInsertPos()->printAsOperand(O, false);
O << ", ";
getAddr()->printAsOperand(O, SlotTracker);
@ -9018,7 +9030,7 @@ void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent,
}
for (unsigned i = 0; i < IG->getFactor(); ++i)
if (Instruction *I = IG->getMember(i))
O << "\\l\" +\n" << Indent << "\" " << VPlanIngredient(I) << " " << i;
O << "\n" << Indent << " " << VPlanIngredient(I) << " " << i;
}
void VPWidenCallRecipe::execute(VPTransformState &State) {

140
lib/Transforms/Vectorize/VPlan.cpp
View File

@ -399,6 +399,42 @@ void VPBasicBlock::dropAllReferences(VPValue *NewValue) {
}
}
void VPBasicBlock::print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const {
O << Indent << getName() << ":\n";
if (const VPValue *Pred = getPredicate()) {
O << Indent << "BlockPredicate:";
Pred->printAsOperand(O, SlotTracker);
if (const auto *PredInst = dyn_cast<VPInstruction>(Pred))
O << " (" << PredInst->getParent()->getName() << ")";
O << '\n';
}
auto RecipeIndent = Indent + " ";
for (const VPRecipeBase &Recipe : *this) {
Recipe.print(O, RecipeIndent, SlotTracker);
O << '\n';
}
if (getSuccessors().empty()) {
O << Indent << "No successors\n";
} else {
O << Indent << "Successor(s): ";
ListSeparator LS;
for (auto *Succ : getSuccessors())
O << LS << Succ->getName();
O << '\n';
}
if (const VPValue *CBV = getCondBit()) {
O << Indent << "CondBit: ";
CBV->printAsOperand(O, SlotTracker);
if (const auto *CBI = dyn_cast<VPInstruction>(CBV))
O << " (" << CBI->getParent()->getName() << ")";
O << '\n';
}
}
void VPRegionBlock::dropAllReferences(VPValue *NewValue) {
for (VPBlockBase *Block : depth_first(Entry))
// Drop all references in VPBasicBlocks and replace all uses with
@ -455,6 +491,17 @@ void VPRegionBlock::execute(VPTransformState *State) {
State->Instance.reset();
}
void VPRegionBlock::print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const {
O << Indent << (isReplicator() ? "<xVFxUF> " : "<x1> ") << getName() << ": {";
auto NewIndent = Indent + " ";
for (auto *BlockBase : depth_first(Entry)) {
O << '\n';
BlockBase->print(O, NewIndent, SlotTracker);
}
O << Indent << "}\n";
}
void VPRecipeBase::insertBefore(VPRecipeBase *InsertPos) {
assert(!Parent && "Recipe already in some VPBasicBlock");
assert(InsertPos->getParent() &&
@ -683,9 +730,28 @@ void VPlan::execute(VPTransformState *State) {
L->getExitBlock());
}
// TODO: Wrap those in #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)/#endif.
LLVM_DUMP_METHOD
void VPlan::print(raw_ostream &O) const {
VPSlotTracker SlotTracker(this);
O << "VPlan {";
for (const VPBlockBase *Block : depth_first(getEntry())) {
O << '\n';
Block->print(O, "", SlotTracker);
}
O << "}\n";
}
LLVM_DUMP_METHOD
void VPlan::printDOT(raw_ostream &O) const {
VPlanPrinter Printer(O, *this);
Printer.dump();
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD
void VPlan::dump() const { dbgs() << *this << '\n'; }
void VPlan::dump() const { print(dbgs()); }
#endif
void VPlan::updateDominatorTree(DominatorTree *DT, BasicBlock *LoopPreHeaderBB,
@ -804,46 +870,32 @@ void VPlanPrinter::dumpEdges(const VPBlockBase *Block) {
}
void VPlanPrinter::dumpBasicBlock(const VPBasicBlock *BasicBlock) {
// Implement dot-formatted dump by performing plain-text dump into the
// temporary storage followed by some post-processing.
OS << Indent << getUID(BasicBlock) << " [label =\n";
bumpIndent(1);
OS << Indent << "\"" << DOT::EscapeString(BasicBlock->getName()) << ":\\n\"";
bumpIndent(1);
std::string Str;
raw_string_ostream SS(Str);
// Use no indentation as we need to wrap the lines into quotes ourselves.
BasicBlock->print(SS, "", SlotTracker);
// Dump the block predicate.
const VPValue *Pred = BasicBlock->getPredicate();
if (Pred) {
OS << " +\n" << Indent << " \"BlockPredicate: \"";
if (const VPInstruction *PredI = dyn_cast<VPInstruction>(Pred)) {
PredI->printAsOperand(OS, SlotTracker);
OS << " (" << DOT::EscapeString(PredI->getParent()->getName())
<< ")\\l\"";
} else
Pred->printAsOperand(OS, SlotTracker);
}
// We need to process each line of the output separately, so split
// single-string plain-text dump.
SmallVector<StringRef, 0> Lines;
StringRef(Str).rtrim('\n').split(Lines, "\n");
for (const VPRecipeBase &Recipe : *BasicBlock) {
OS << " +\n" << Indent << "\"";
// Don't indent inside the recipe printer as we printed it before the
// opening quote already.
Recipe.print(OS, "", SlotTracker);
OS << "\\l\"";
}
auto EmitLine = [&](StringRef Line, StringRef Suffix) {
OS << Indent << '"' << DOT::EscapeString(Line.str()) << "\\l\"" << Suffix;
};
// Dump the condition bit.
const VPValue *CBV = BasicBlock->getCondBit();
if (CBV) {
OS << " +\n" << Indent << " \"CondBit: ";
if (const VPInstruction *CBI = dyn_cast<VPInstruction>(CBV)) {
CBI->printAsOperand(OS, SlotTracker);
OS << " (" << DOT::EscapeString(CBI->getParent()->getName()) << ")\\l\"";
} else {
CBV->printAsOperand(OS, SlotTracker);
OS << "\"";
}
}
// Don't need the "+" after the last line.
for (auto Line : make_range(Lines.begin(), Lines.end() - 1))
EmitLine(Line, " +\n");
EmitLine(Lines.back(), "\n");
bumpIndent(-1);
OS << Indent << "]\n";
bumpIndent(-2);
OS << "\n" << Indent << "]\n";
dumpEdges(BasicBlock);
}
@ -863,25 +915,21 @@ void VPlanPrinter::dumpRegion(const VPRegionBlock *Region) {
dumpEdges(Region);
}
void VPlanPrinter::printAsIngredient(raw_ostream &O, const Value *V) {
std::string IngredientString;
raw_string_ostream RSO(IngredientString);
void VPlanIngredient::print(raw_ostream &O) const {
if (auto *Inst = dyn_cast<Instruction>(V)) {
if (!Inst->getType()->isVoidTy()) {
Inst->printAsOperand(RSO, false);
RSO << " = ";
Inst->printAsOperand(O, false);
O << " = ";
}
RSO << Inst->getOpcodeName() << " ";
O << Inst->getOpcodeName() << " ";
unsigned E = Inst->getNumOperands();
if (E > 0) {
Inst->getOperand(0)->printAsOperand(RSO, false);
Inst->getOperand(0)->printAsOperand(O, false);
for (unsigned I = 1; I < E; ++I)
Inst->getOperand(I)->printAsOperand(RSO << ", ", false);
Inst->getOperand(I)->printAsOperand(O << ", ", false);
}
} else // !Inst
V->printAsOperand(RSO, false);
RSO.flush();
O << DOT::EscapeString(IngredientString);
V->printAsOperand(O, false);
}
void VPWidenCallRecipe::print(raw_ostream &O, const Twine &Indent,

73
lib/Transforms/Vectorize/VPlan.h
View File

@ -577,12 +577,6 @@ public:
OS << getName();
}
void print(raw_ostream &OS) const {
// TODO: Only printing VPBB name for now since we only have dot printing
// support for VPInstructions/Recipes.
printAsOperand(OS, false);
}
/// Return true if it is legal to hoist instructions into this block.
bool isLegalToHoistInto() {
// There are currently no constraints that prevent an instruction to be
@ -593,6 +587,24 @@ public:
/// Replace all operands of VPUsers in the block with \p NewValue and also
/// replaces all uses of VPValues defined in the block with NewValue.
virtual void dropAllReferences(VPValue *NewValue) = 0;
/// Print plain-text dump of this VPBlockBase to \p O, prefixing all lines
/// with \p Indent. \p SlotTracker is used to print unnamed VPValue's using
/// consequtive numbers.
///
/// Note that the numbering is applied to the whole VPlan, so printing
/// individual blocks is consistent with the whole VPlan printing.
virtual void print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const = 0;
/// Print plain-text dump of this VPlan to \p O.
void print(raw_ostream &O) const {
VPSlotTracker SlotTracker(getPlan());
print(O, "", SlotTracker);
}
/// Dump this VPBlockBase to dbgs().
void dump() const { print(dbgs()); }
};
/// VPRecipeBase is a base class modeling a sequence of one or more output IR
@ -1246,12 +1258,11 @@ public:
/// Print the recipe.
void print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const override {
O << " +\n" << Indent << "\"BRANCH-ON-MASK ";
O << Indent << "BRANCH-ON-MASK ";
if (VPValue *Mask = getMask())
Mask->printAsOperand(O, SlotTracker);
else
O << " All-One";
O << "\\l\"";
}
/// Return the mask used by this recipe. Note that a full mask is represented
@ -1463,6 +1474,15 @@ public:
void dropAllReferences(VPValue *NewValue) override;
/// Print this VPBsicBlock to \p O, prefixing all lines with \p Indent. \p
/// SlotTracker is used to print unnamed VPValue's using consequtive numbers.
///
/// Note that the numbering is applied to the whole VPlan, so printing
/// individual blocks is consistent with the whole VPlan printing.
void print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const override;
using VPBlockBase::print; // Get the print(raw_stream &O) version.
private:
/// Create an IR BasicBlock to hold the output instructions generated by this
/// VPBasicBlock, and return it. Update the CFGState accordingly.
@ -1554,6 +1574,16 @@ public:
void execute(struct VPTransformState *State) override;
void dropAllReferences(VPValue *NewValue) override;
/// Print this VPRegionBlock to \p O (recursively), prefixing all lines with
/// \p Indent. \p SlotTracker is used to print unnamed VPValue's using
/// consequtive numbers.
///
/// Note that the numbering is applied to the whole VPlan, so printing
/// individual regions is consistent with the whole VPlan printing.
void print(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const override;
using VPBlockBase::print; // Get the print(raw_stream &O) version.
};
//===----------------------------------------------------------------------===//
@ -1806,6 +1836,12 @@ public:
VPLoopInfo &getVPLoopInfo() { return VPLInfo; }
const VPLoopInfo &getVPLoopInfo() const { return VPLInfo; }
/// Print this VPlan to \p O.
void print(raw_ostream &O) const;
/// Print this VPlan in DOT format to \p O.
void printDOT(raw_ostream &O) const;
/// Dump the plan to stderr (for debugging).
void dump() const;
@ -1830,11 +1866,6 @@ private:
/// VPlanPrinter prints a given VPlan to a given output stream. The printing is
/// indented and follows the dot format.
class VPlanPrinter {
friend inline raw_ostream &operator<<(raw_ostream &OS, const VPlan &Plan);
friend inline raw_ostream &operator<<(raw_ostream &OS,
const struct VPlanIngredient &I);
private:
raw_ostream &OS;
const VPlan &Plan;
unsigned Depth = 0;
@ -1845,9 +1876,6 @@ private:
VPSlotTracker SlotTracker;
VPlanPrinter(raw_ostream &O, const VPlan &P)
: OS(O), Plan(P), SlotTracker(&P) {}
/// Handle indentation.
void bumpIndent(int b) { Indent = std::string((Depth += b) * TabWidth, ' '); }
@ -1877,25 +1905,28 @@ private:
void drawEdge(const VPBlockBase *From, const VPBlockBase *To, bool Hidden,
const Twine &Label);
void dump();
public:
VPlanPrinter(raw_ostream &O, const VPlan &P)
: OS(O), Plan(P), SlotTracker(&P) {}
static void printAsIngredient(raw_ostream &O, const Value *V);
void dump();
};
struct VPlanIngredient {
const Value *V;
VPlanIngredient(const Value *V) : V(V) {}
void print(raw_ostream &O) const;
};
inline raw_ostream &operator<<(raw_ostream &OS, const VPlanIngredient &I) {
VPlanPrinter::printAsIngredient(OS, I.V);
I.print(OS);
return OS;
}
inline raw_ostream &operator<<(raw_ostream &OS, const VPlan &Plan) {
VPlanPrinter Printer(OS, Plan);
Printer.dump();
Plan.print(OS);
return OS;
}

13
test/Transforms/LoopVectorize/icmp-uniforms.ll
View File

@ -36,12 +36,13 @@ for.end:
}
; Check for crash exposed by D76992.
; CHECK: N0 [label =
; CHECK-NEXT: "loop:\n" +
; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi 0, %iv.next\l" +
; CHECK-NEXT: "WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>\l" +
; CHECK-NEXT: "WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>\l"
; CHECK-NEXT: ]
; CHECK: VPlan {
; CHECK-NEXT: loop:
; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next
; CHECK-NEXT: WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>
; CHECK-NEXT: WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>
; CHECK-NEXT: No successor
; CHECK-NEXT: }
define void @test() {
entry:
br label %loop

40
test/Transforms/LoopVectorize/vplan-dot-printing.ll Normal file
View File

@ -0,0 +1,40 @@
; REQUIRES: asserts
; RUN: opt -loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -vplan-print-in-dot-format -disable-output %s 2>&1 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
; Verify that -vplan-print-in-dot-format option works.
define void @print_call_and_memory(i64 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
; CHECK: N0 [label =
; CHECK-NEXT: "for.body:\l" +
; CHECK-NEXT: " WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
; CHECK-NEXT: " CLONE ir\<%arrayidx\> = getelementptr ir\<%y\>, ir\<%iv\>\l" +
; CHECK-NEXT: " WIDEN ir\<%lv\> = load ir\<%arrayidx\>\l" +
; CHECK-NEXT: " WIDEN-CALL ir\<%call\> = call @llvm.sqrt.f32(ir\<%lv\>)\l" +
; CHECK-NEXT: " CLONE ir\<%arrayidx2\> = getelementptr ir\<%x\>, ir\<%iv\>\l" +
; CHECK-NEXT: " WIDEN store ir\<%arrayidx2\>, ir\<%call\>\l" +
; CHECK-NEXT: "No successors\l"
; CHECK-NEXT: ]
;
entry:
%cmp6 = icmp sgt i64 %n, 0
br i1 %cmp6, label %for.body, label %for.end
for.body: ; preds = %entry, %for.body
%iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds float, float* %y, i64 %iv
%lv = load float, float* %arrayidx, align 4
%call = tail call float @llvm.sqrt.f32(float %lv) nounwind readnone
%arrayidx2 = getelementptr inbounds float, float* %x, i64 %iv
store float %call, float* %arrayidx2, align 4
%iv.next = add i64 %iv, 1
%exitcond = icmp eq i64 %iv.next, %n
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
ret void
}
declare float @llvm.sqrt.f32(float) nounwind readnone

129
test/Transforms/LoopVectorize/vplan-printing.ll
View File

@ -7,16 +7,17 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; Tests for printing VPlans.
define void @print_call_and_memory(i64 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
; CHECK: N0 [label =
; CHECK-NEXT: "for.body:\n" +
; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
; CHECK-NEXT: "CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" +
; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" +
; CHECK-NEXT: "WIDEN-CALL ir<%call> = call @llvm.sqrt.f32(ir<%lv>)\l" +
; CHECK-NEXT: "CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>\l" +
; CHECK-NEXT: "WIDEN store ir<%arrayidx2>, ir<%call>\l"
; CHECK-NEXT: ]
; CHECK: VPlan {
; CHECK-NEXT: for.body:
; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, 0
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>
; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx>
; CHECK-NEXT: WIDEN-CALL ir<%call> = call @llvm.sqrt.f32(ir<%lv>)
; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>
; CHECK-NEXT: WIDEN store ir<%arrayidx2>, ir<%call>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
%cmp6 = icmp sgt i64 %n, 0
br i1 %cmp6, label %for.body, label %for.end
@ -37,18 +38,19 @@ for.end: ; preds = %for.body, %entry
}
define void @print_widen_gep_and_select(i64 %n, float* noalias %y, float* noalias %x, float* %z) nounwind uwtable {
; CHECK: N0 [label =
; CHECK-NEXT: "for.body:\n" +
; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
; CHECK-NEXT: "WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" +
; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" +
; CHECK-NEXT: "WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z>\l" +
; CHECK-NEXT: "WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01>\l" +
; CHECK-NEXT: "WIDEN ir<%add> = fadd ir<%lv>, ir<%sel>\l" +
; CHECK-NEXT: "CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>\l" +
; CHECK-NEXT: "WIDEN store ir<%arrayidx2>, ir<%add>\l"
; CHECK-NEXT: ]
; CHECK: VPlan {
; CHECK-NEXT: for.body:
; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, 0
; CHECK-NEXT: WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>
; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx>
; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z>
; CHECK-NEXT: WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01>
; CHECK-NEXT: WIDEN ir<%add> = fadd ir<%lv>, ir<%sel>
; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>
; CHECK-NEXT: WIDEN store ir<%arrayidx2>, ir<%add>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
%cmp6 = icmp sgt i64 %n, 0
br i1 %cmp6, label %for.body, label %for.end
@ -71,15 +73,16 @@ for.end: ; preds = %for.body, %entry
}
define float @print_reduction(i64 %n, float* noalias %y) {
; CHECK: N0 [label =
; CHECK-NEXT: "for.body:\n" +
; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" +
; CHECK-NEXT: "WIDEN-PHI %red = phi %red.next, 0.000000e+00\l" +
; CHECK-NEXT: "CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" +
; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" +
; CHECK-NEXT: "REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>)\l"
; CHECK-NEXT: ]
; CHECK: VPlan {
; CHECK-NEXT: for.body:
; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, 0
; CHECK-NEXT: WIDEN-PHI %red = phi %red.next, 0.000000e+00
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>
; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx>
; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>)
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %for.body
@ -98,36 +101,40 @@ for.end: ; preds = %for.body, %entry
}
define void @print_replicate_predicated_phi(i64 %n, i64* %x) {
; CHECK: N0 [label =
; CHECK-NEXT: "for.body:\n" +
; CHECK-NEXT: "WIDEN-INDUCTION %i = phi 0, %i.next\l" +
; CHECK-NEXT: "WIDEN ir<%cmp> = icmp ir<%i>, ir<5>\l"
; CHECK-NEXT: ]
;
; CHECK: N2 [label =
; CHECK-NEXT: "pred.udiv.entry:\n" +
; CHECK-NEXT: +
; CHECK-NEXT: "BRANCH-ON-MASK ir<%cmp>\l"\l
; CHECK-NEXT: "CondBit: ir<%cmp>"
; CHECK-NEXT: ]
;
; CHECK: N4 [label =
; CHECK-NEXT: "pred.udiv.if:\n" +
; CHECK-NEXT: "REPLICATE ir<%tmp4> = udiv ir<%n>, ir<%i> (S->V)\l"
; CHECK-NEXT: ]
;
; CHECK: N5 [label =
; CHECK-NEXT: "pred.udiv.continue:\n" +
; CHECK-NEXT: "PHI-PREDICATED-INSTRUCTION vp<%3> = ir<%tmp4>\l"
; CHECK-NEXT: ]
;
; CHECK: N7 [label =
; CHECK-NEXT: "for.inc:\n" +
; CHECK-NEXT: "EMIT vp<%4> = not ir<%cmp>\l" +
; CHECK-NEXT: "BLEND %d = ir<0>/vp<%4> vp<%3>/ir<%cmp>\l" +
; CHECK-NEXT: "CLONE ir<%idx> = getelementptr ir<%x>, ir<%i>\l" +
; CHECK-NEXT: "WIDEN store ir<%idx>, ir<%d>\l"
; CHECK-NEXT: ]
; CHECK: VPlan {
; CHECK-NEXT: for.body:
; CHECK-NEXT: WIDEN-INDUCTION %i = phi 0, %i.next
; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%i>, ir<5>
; CHECK-NEXT: Successor(s): if.then
; CHECK-EMPTY:
; CHECK-NEXT: if.then:
; CHECK-NEXT: Successor(s): pred.udiv
; CHECK-EMPTY:
; CHECK-NEXT: <xVFxUF> pred.udiv: {
; CHECK-NEXT: pred.udiv.entry:
; CHECK-NEXT: BRANCH-ON-MASK ir<%cmp>
; CHECK-NEXT: Successor(s): pred.udiv.if, pred.udiv.continue
; CHECK-NEXT: CondBit: ir<%cmp>
; CHECK-EMPTY:
; CHECK-NEXT: pred.udiv.if:
; CHECK-NEXT: REPLICATE ir<%tmp4> = udiv ir<%n>, ir<%i> (S->V)
; CHECK-NEXT: Successor(s): pred.udiv.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.udiv.continue:
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%3> = ir<%tmp4>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-EMPTY:
; CHECK-NEXT: if.then.0:
; CHECK-NEXT: Successor(s): for.inc
; CHECK-EMPTY:
; CHECK-NEXT: for.inc:
; CHECK-NEXT: EMIT vp<%4> = not ir<%cmp>
; CHECK-NEXT: BLEND %d = ir<0>/vp<%4> vp<%3>/ir<%cmp>
; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%x>, ir<%i>
; CHECK-NEXT: WIDEN store ir<%idx>, ir<%d>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %for.body

30
unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
View File

@ -93,7 +93,8 @@ TEST_F(VPlanHCFGTest, testBuildHCFGInnerLoop) {
// as this is not required with the new printing.
Plan->addVPValue(&*F->arg_begin());
std::string FullDump;
raw_string_ostream(FullDump) << *Plan;
raw_string_ostream OS(FullDump);
Plan->printDOT(OS);
const char *ExpectedStr = R"(digraph VPlan {
graph [labelloc=t, fontsize=30; label="Vectorization Plan"]
node [shape=rect, fontname=Courier, fontsize=30]
@ -103,25 +104,28 @@ compound=true
fontname=Courier
label="\<x1\> TopRegion"
N1 [label =
"entry:\n"
"entry:\l" +
"Successor(s): for.body\l"
]
N1 -> N2 [ label=""]
N2 [label =
"for.body:\n" +
"WIDEN-PHI %indvars.iv = phi 0, %indvars.iv.next\l" +
"EMIT ir<%arr.idx> = getelementptr ir<%A> ir<%indvars.iv>\l" +
"EMIT ir<%l1> = load ir<%arr.idx>\l" +
"EMIT ir<%res> = add ir<%l1> ir<10>\l" +
"EMIT store ir<%res> ir<%arr.idx>\l" +
"EMIT ir<%indvars.iv.next> = add ir<%indvars.iv> ir<1>\l" +
"EMIT ir<%exitcond> = icmp ir<%indvars.iv.next> ir<%N>\l" +
"CondBit: ir<%exitcond> (for.body)\l"
"for.body:\l" +
" WIDEN-PHI %indvars.iv = phi 0, %indvars.iv.next\l" +
" EMIT ir\<%arr.idx\> = getelementptr ir\<%A\> ir\<%indvars.iv\>\l" +
" EMIT ir\<%l1\> = load ir\<%arr.idx\>\l" +
" EMIT ir\<%res\> = add ir\<%l1\> ir\<10\>\l" +
" EMIT store ir\<%res\> ir\<%arr.idx\>\l" +
" EMIT ir\<%indvars.iv.next\> = add ir\<%indvars.iv\> ir\<1\>\l" +
" EMIT ir\<%exitcond\> = icmp ir\<%indvars.iv.next\> ir\<%N\>\l" +
"Successor(s): for.body, for.end\l" +
"CondBit: ir\<%exitcond\> (for.body)\l"
]
N2 -> N2 [ label="T"]
N2 -> N3 [ label="F"]
N3 [label =
"for.end:\n" +
"EMIT ret\l"
"for.end:\l" +
" EMIT ret\l" +
"No successors\l"
]
}
}

43
unittests/Transforms/Vectorize/VPlanTest.cpp
View File

@ -333,12 +333,14 @@ TEST(VPBasicBlockTest, print) {
VPBB1->appendRecipe(I1);
VPBB1->appendRecipe(I2);
VPBB1->appendRecipe(I3);
VPBB1->setName("bb1");
VPInstruction *I4 = new VPInstruction(Instruction::Mul, {I2, I1});
VPInstruction *I5 = new VPInstruction(Instruction::Ret, {I4});
VPBasicBlock *VPBB2 = new VPBasicBlock();
VPBB2->appendRecipe(I4);
VPBB2->appendRecipe(I5);
VPBB2->setName("bb2");
VPBlockUtils::connectBlocks(VPBB1, VPBB2);
@ -355,7 +357,8 @@ TEST(VPBasicBlockTest, print) {
VPlan Plan;
Plan.setEntry(VPBB1);
std::string FullDump;
raw_string_ostream(FullDump) << Plan;
raw_string_ostream OS(FullDump);
Plan.printDOT(OS);
const char *ExpectedStr = R"(digraph VPlan {
graph [labelloc=t, fontsize=30; label="Vectorization Plan"]
@ -363,21 +366,45 @@ node [shape=rect, fontname=Courier, fontsize=30]
edge [fontname=Courier, fontsize=30]
compound=true
N0 [label =
":\n" +
"EMIT vp<%0> = add\l" +
"EMIT vp<%1> = sub vp<%0>\l" +
"EMIT br vp<%0> vp<%1>\l"
"bb1:\l" +
" EMIT vp\<%0\> = add\l" +
" EMIT vp\<%1\> = sub vp\<%0\>\l" +
" EMIT br vp\<%0\> vp\<%1\>\l" +
"Successor(s): bb2\l"
]
N0 -> N1 [ label=""]
N1 [label =
":\n" +
"EMIT vp<%3> = mul vp<%1> vp<%0>\l" +
"EMIT ret vp<%3>\l"
"bb2:\l" +
" EMIT vp\<%3\> = mul vp\<%1\> vp\<%0\>\l" +
" EMIT ret vp\<%3\>\l" +
"No successors\l"
]
}
)";
EXPECT_EQ(ExpectedStr, FullDump);
const char *ExpectedBlock1Str = R"(bb1:
EMIT vp<%0> = add
EMIT vp<%1> = sub vp<%0>
EMIT br vp<%0> vp<%1>
Successor(s): bb2
)";
std::string Block1Dump;
raw_string_ostream OS1(Block1Dump);
VPBB1->print(OS1);
EXPECT_EQ(ExpectedBlock1Str, Block1Dump);
// Ensure that numbering is good when dumping the second block in isolation.
const char *ExpectedBlock2Str = R"(bb2:
EMIT vp<%3> = mul vp<%1> vp<%0>
EMIT ret vp<%3>
No successors
)";
std::string Block2Dump;
raw_string_ostream OS2(Block2Dump);
VPBB2->print(OS2);
EXPECT_EQ(ExpectedBlock2Str, Block2Dump);
{
std::string I3Dump;
raw_string_ostream OS(I3Dump);