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Adjust offsets for max load instruction offsets. This is more pessimistic

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than it needs to be by 1 bit but I need to finish some other things so 
that all the boundary cases will work in that situation. constpool.c
in test-suite will fail to assemble under our new internal test-suite sync
without this change.

llvm-svn: 199343
This commit is contained in:
Reed Kotler 2014-01-16 00:47:46 +00:00
parent 3da161096a
commit c3cb7dce9b
3 changed files with 5 additions and 3 deletions
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2
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -119,6 +119,7 @@ class FJAL16_ins<bits<1> _X, string asmstr,
!strconcat(asmstr, "\t$imm\n\tnop"),[],
itin> {
let isCodeGenOnly=1;
let Size=6;
}
class FJALB16_ins<bits<1> _X, string asmstr,
@ -127,6 +128,7 @@ class FJALB16_ins<bits<1> _X, string asmstr,
!strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
itin> {
let isCodeGenOnly=1;
let Size=6;
}
//

4
lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -790,11 +790,11 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
Bits = 8;
Scale = 4;
LongFormOpcode = Mips::LwRxPcTcpX16;
LongFormBits = 16;
LongFormBits = 14;
LongFormScale = 1;
break;
case Mips::LwRxPcTcpX16:
Bits = 16;
Bits = 14;
Scale = 1;
NegOk = true;
break;

2
test/CodeGen/Mips/const6a.ll
View File

@ -19,7 +19,7 @@ entry:
; load-relax: $CPI0_0:
; load-relax: .4byte 3735943886
; load-relax: .end t
call void asm sideeffect ".space 40000", ""() #1, !srcloc !1
call void asm sideeffect ".space 10000", ""() #1, !srcloc !1
ret void
}